EP80579 Datasheet, PDF (1150/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
31.5
Reading from the Interval Timer
It is often desirable to read the value of a counter without disturbing the count in
progress. There are three methods for reading the counters: a Simple Read operation,
Counter Latch command, and the Read-Back command. Each is explained in the
following sections.
With the Simple Read and Counter Latch command methods, the count must be read
according to the programmed format; specifically, if the counter is programmed for two
byte counts, two bytes must be read. The two bytes do not have to be read
sequentially. Read, write, or programming operations for other counters may be
inserted between them.
31.5.1
Simple Read
The first method is to perform a simple read operation. The counter is selected through
port 40h (counter 0), 41h (counter 1), or 42h (counter 2).
Note:
Performing a direct read from the counter does not return a determinate value,
because the counting process is asynchronous to read operations. However, in the case
of counter 2, the count can be stopped by writing to the GATE bit in port 61h.
31.5.2 Counter Latch Command
The Counter Latch Command (Table 31-7), written to port 43h, latches the count of a
specific counter at the time the command is received. This command is used to ensure
that the count read from the counter is accurate, particularly when reading a two-byte
count. The count value is then read from each counter's Count Register through the
Counter Port’s Access Ports Register (40h for counter 0, 41h for counter 1, and 42h for
counter 2).
The count is held in the latch until it is read or the counter is reprogrammed. The count
is then unlatched. This allows reading the contents of the counters on the fly without
affecting counting in progress. Multiple Counter Latch commands may be used to latch
more than one counter. Counter Latch commands do not affect the programmed mode
of the counter in any way.
If a counter is latched and then, some time later, latched again before the count is
read, the second Counter Latch command is ignored. The count read is the count at the
time the first Counter Latch command was issued.
Table 31-7. Counter Latch Command
Bits
07:06
05:04
03:00
Description
Counter Selection: These bits select the counter for latching.
00 Counter 0
01 Counter 1
10 Counter 2
11 The write is interpreted as a read back command.
Counter Latch Command: Write ‘00’ to select the Counter Latch Command.
Reserved. Must be 0.
Intel^® EP80579 Integrated Processor Product Line Datasheet
1150
August 2009
Order Number: 320066-003US