EP80579 Datasheet, PDF (524/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 16-138.Bus 0, Device 2, Function 0: Summary of PCI Express Port A Standard and
Enhanced PCI Configuration Registers (Sheet 3 of 3)
Offset Start Offset End
Register ID - Description
Default
Value
14Ch
150h
158h
160h
164h
168h
14Fh
153h
15Bh
163h
167h
16Bh
“Offset 14Ch: UNCEDMASK - Uncorrectable Error Detect Mask Register” on
page 591
00000000h
“Offset 150h: COREDMASK - Correctable Error Detect Mask Register” on page 592 00000000h
“Offset 158h: PEAUNITEDMASK - PCI Express Unit Error Detect Mask Register” on
page 594
00000000h
“Offset 160h: PEAFERR - PCI Express First Error Register” on page 595
00000000h
“Offset 164h: PEANERR - PCI Express Next Error Register” on page 597
00000000h
“Offset 168h: PEAERRINJCTL - Error Injection Control Register” on page 597
00000000h
Table 16-139.Bus 0, Device 3, Function 0: Summary of PCI Express Port A1 Standard and
Enhanced PCI Configuration Registers (Sheet 1 of 3)
Offset Start Offset End
Register ID - Description
Default
Value
00h
02h
04h
06h
08h
0Ah
0Bh
0Ch
0Eh
18h
19h
1Ah
1Ch
1Dh
1Eh
20h
22h
24h
26h
28h
2Ch
34h
3Ch
3Dh
3Eh
01h
03h
05h
07h
08h
0Ah
0Bh
0Ch
0Eh
18h
19h
1Ah
1Ch
1Dh
1Fh
21h
23h
25h
27h
28h
2Ch
34h
3Ch
3Dh
3Eh
“Offset 00h: VID - Vendor Identification Register” on page 527
8086h
“Offset 02h: DID - Device Identification Register” on page 528
5025h
“Offset 04h: PCICMD - PCI Command Register” on page 528
0000h
“Offset 06h: PCISTS - PCI Status Register” on page 530
0010h
“Offset 08h: RID - Revision Identification Register” on page 531
Variable
“Offset 0Ah: SUBC - Sub-Class Code Register” on page 532
04h
“Offset 0Bh: BCC - Base Class Code Register” on page 532
06h
“Offset 0Ch: CLS - Cache Line Size Register” on page 533
00h
“Offset 0Eh: HDR - Header Type Register” on page 533
01h
“Offset 18h: PBUSN - Primary Bus Number Register” on page 534
00h
“Offset 19h: SBUSN - Secondary Bus Number Register” on page 534
00h
“Offset 1Ah: SUBUSN: Subordinate Bus Number Register” on page 535
00h
“Offset 1Ch: IOBASE - I/O Base Address Register” on page 535
F0h
“Offset 1Dh: IOLIMIT - I/O Limit Address Register” on page 536
00h
“Offset 1Eh: SECSTS - Secondary Status Register” on page 536
0000h
“Offset 20h: MBASE - Memory Base Address Register” on page 538
FFF0h
“Offset 22h: MLIMIT - Memory Limit Address Register” on page 539
0000h
“Offset 24h: PMBASE - Prefetchable Memory Base Address Register” on page 540 FFF1h
“Offset 26h: PMLIMIT - Prefetchable Memory Limit Address Register” on page 540 0001h
“Offset 28h: PMBASU - Prefetchable Memory Base Upper Address Register” on
page 541
0Fh
“Offset 2Ch: PMLMTU - Prefetchable Memory Limit Upper Address Register” on
page 541
00h
“Offset 34h: CAPPTR - Capabilities Pointer Register” on page 542
50h
“Offset 3Ch: INTRLINE - Interrupt Line Register” on page 542
00h
“Offset 3Dh: INTRPIN - Interrupt Pin Register” on page 543
01h
“Offset 3Eh: BCTRL - Bridge Control Register” on page 543
00h
Intel^® EP80579 Integrated Processor Product Line Datasheet
524
August 2009
Order Number: 320066-003US