EP80579 Datasheet, PDF (1196/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
33.6.2.4 Offset 04h: PV2R0 - Preload Value 2 Register 0
Table 33-29. Offset 04h: PV2R0 - Preload Value 2 Register 0
Description:
View: IA F
Base Address: Base (IO)
Offset Start: 04h
Offset End: 04h
Size: 8 bit
Default: FFh
Power Well: Core
Bit Range
07 : 00
Bit Acronym
Bit Description
Sticky
PLOAD2_7_0
Preload_Value_2 [7:0]: This register is used to hold the
bits 0 through 7 of the preload value2 for the WDT Timer.
The Value in the Preload Register is automatically
transferred into the 35-bit down counter every time the
WDT enters the second stage.
The value loaded into the preload register needs to be one
less than the intended period. This is because the timer
makes use of zero-based counting (i.e., zero is counted as
part of the decrement).
Refer to Section 33.6.3.2 for details on how to change the
value of this register.
Bit Reset
Value
FFh
Bit Access
RW
33.6.2.5 Offset 05h: PV2R1 - Preload Value 2 Register 1
Table 33-30. Offset 05h: PV2R1 - Preload Value 2 Register 1
Description:
View: IA F
Base Address: Base (IO)
Offset Start: 05h
Offset End: 05h
Size: 8 bit
Default: FFh
Power Well: Core
Bit Range
07 : 00
Bit Acronym
Bit Description
Sticky
Preload_Value_2 [15:8]: This register is used to hold
the bits 8 through 15 of the preload value2 for the WDT
Timer. The Value in the Preload Register is automatically
transferred into the 35-bit down counter every time the
WDT enters the second stage.
PLOAD2_15_8 The value loaded into the preload register needs to be one
less than the intended period. This is because the timer
makes use of zero-based counting (i.e., zero is counted as
part of the decrement).
Refer to Section 33.6.3.2 for details on how to change the
value of this register.
Bit Reset
Value
FFh
Bit Access
RW
Intel^® EP80579 Integrated Processor Product Line Datasheet
1196
August 2009
Order Number: 320066-003US