EP80579 Datasheet, PDF (1444/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
37.6.2.4
CTRL_AUX – Auxiliary Device Control/Status Register
This register provides extended control of device functionality beyond that provided by
the Device Control Register (CTRL) and Extended Device Control Register
Table 37-28. CTRL_AUX: Auxiliary Device Control Register (Sheet 1 of 2)
Description:
View: PCI 1
BAR: CSRBAR
Bus:Device:Function: M:0:0
Offset Start: 00E0h
Offset End: 00E3h
View: PCI 2
BAR: CSRBAR
Bus:Device:Function: M:1:0
Offset Start: 00E0h
Offset End: 00E3h
View: PCI 3
BAR: CSRBAR
Bus:Device:Function: M:2:0
Offset Start: 00E0h
Offset End: 00E3h
Size: 32 bits
Default: 00000100h
GbE0: Aux
Power Well: Gbe1/2:
Core
Bit Range Bit Acronym
Bit Description
Sticky
31 :18
17
16
15 :12
11 :10
RSVD
Reserved
Enable logic change to fix RMII 100mbps TX dropped
packet data.
To enable this mode of operation, set this bit to a ‘1’. When
RMII_LOG_FIX enabled, the fix modifies the legacy new-packet signalling
logic in the transmit path to prevent the first 8 bytes of
packet data from being dropped when operating in RMII
mode and a line speed of 100mbps.
Disable DMA frequency change to fix RMII 100mbps TX
dropped packet data.
This is the default mode of operation.
To disable this mode of operation, set this bit to a ‘1’. This
must be disabled if FIX2 is enabled.
RMII_FREQ_FIX _{When enabled, sets the DMA clock frequency to 50MHz}
when operating in RMII mode. This produces a favorable
frequency ratio between DMA and MAC clocks that
prevents the first 8 bytes of transmit packet data from
being dropped when operating in RMII mode and a line
speed of 100mbps.
RSVD
Reserved
END_SEL
Selects whether the descriptor or packet data is controlled
by endianness configuration.
00 - descriptor and packet transfers use
CTRL_AUX.ENDIANESS
01 - descriptor uses CTL_AUX.ENDIANESS, packet uses
default
10 - descriptor uses default, packet uses
CTRL_AUX.ENDIANESS
11 - all transfers use CTRL_AUX.ENDIANESS
Bit Reset
Value
0h
0h
0h
0h
0h
Bit Access
RO
RW
RW
RO
RW
Intel^® EP80579 Integrated Processor Product Line Datasheet
1444
August 2009
Order Number: 320066-003US