EP80579 Datasheet, PDF (479/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
16.2.1.32 Offset 7Ch: BUF_SERRCMD - Memory Buffer SERR Command Register
This register enables various errors to generate an SERR NSI special cycle. When an
error flag is set in the FERR or NERR registers, it generates an SERR NSI special cycle
when enabled in the SERRCMD register. Note that one and only one message type can
be enabled.
Table 16-86. Offset 7Ch: BUF_SERRCMD - Memory Buffer SERR Command Register
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:0:1
Offset Start: 7Ch
Offset End: 7Ch
Size: 8 bit
Default: 00h
Power Well: Core
Bit Range Bit Acronym
Bit Description
Sticky
07 : 04
03
02
01
00
Reserved Reserved
Internal DRAM II/F to PMWB Parity Error SERR
Enable: Generate SERR when parity error detected for
DPMWB_SERR ^{DRAM I/F to PMWB when this bit is set.}
0 = Disable
1 = Enable
Internal System Bus or I/O to PMWB Parity Error
SERR Enable: Generate SERR when parity error detected
IOPMWB_SERR ^{on write port 0 when this bit is set.}
0 = Disable
1 = Enable
Internal PMWB to System Bus Parity Error SERR
Enable: Generate SERR when parity error detected for
PMWBSYS_SER _{PMWB to System Bus when this bit is set.}
R
0 = Disable
1 = Enable
Internal PMWB to DRAM I/F Parity Error SERR
Enable: Generate SERR when parity error detected for
PMWBD_SERR ^{PMWB to DRAM I/F when this bit is set.}
0 = Disable
1 = Enable
Bit Reset
Value
0h
0b
0b
0b
0b
Bit Access
RW
RW
RW
RW
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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