EP80579 Datasheet, PDF (575/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
16.4.1.61 Offset 10Ch: UNCERRSEV - Uncorrectable Error Severity Register
The Uncorrectable Error Severity register controls whether an individual error is
reported as a nonfatal or fatal error. An error is reported as fatal when the
corresponding error bit in the severity register is set. If the bit is cleared, the
corresponding error is considered nonfatal. These bits are sticky through reset.
Table 16-200.Offset 10Ch: UNCERRSEV - Uncorrectable Error Severity Register (Sheet 1 of
2)
Description:
View: PCI 1
BAR: Configuration
Bus:Device:Function: 0:2:0
Offset Start: 10Ch
Offset End: 10Fh
View: PCI 2
BAR: Configuration
Bus:Device:Function: 0:3:0
Offset Start: 10Ch
Offset End: 10Fh
Size: 32 bit
Default: 00062010h
Power Well: Core
Bit Range Bit Acronym
Bit Description
31 : 21
20
Reserved Reserved
Unsupported Request:
USR_UNCERRS 0 = Nonfatal
EV
1 = Fatal
Sticky
Bit Reset
Value
000h
Bit Access
Y
0b
RW
19
EESEV
ECRC Error Severity:
Note: ECRC is not supported for the EP80579.
Malformed TLP Severity:
18
MTSEV
0 = Nonfatal
1 = Fatal
Y
0b
RO
Y
1b
RW
Receiver Overflow Severity: Optional PCI Express*
specification bit, implemented for IMCH.
17
ROSEV
0 = Nonfatal
1 = Fatal
Y
1b
RW
Unexpected Completion Severity:
16
UCSEV
0 = Nonfatal
1 = Fatal
Y
0b
RW
Completer Abort Severity [STICKY]: Optional PCI
Express* specification bit, implemented for IMCH.
15
CASEV
0 = Nonfatal
1 = Fatal
Y
0b
RW
Completion Timeout Severity:
14
CTSEV
0 = Nonfatal
1 = Fatal
Y
0b
RW
Flow Control Protocol Error Severity: Optional PCI
Express* specification bit, implemented for IMCH.
13
FCPESEV 0 = Nonfatal
1 = Fatal
Y
1b
RW
Poisoned TLP Severity:
12
PTSEV
0 = Nonfatal
1 = Fatal
Y
0b
RW
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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