EP80579 Datasheet, PDF (261/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
9.5.3
• APIC and MSI interrupt messaging support DMA internal score-boarding to
translate messages into level-sensitive IICH pin semantics
— XTPR-based interrupt redirection for APIC messages with lowest priority tie
breaking
• Support for up to 256B read completion combining
• Support for link messaging to facilitate active link and device power state
management
• Support for ASPM L0s entry, no support for optional L1 ASPM support
• No support for inbound configuration or I/O traffic
• No support for inbound special cycles or writes requiring completions
• No support for downstream special cycle messages requiring completions
EDMA Controller
• Four Independent Channels
— Dedicated data transfer queue per channel
— Full register set for descriptor and transfer handling per channel
• Support for transfer between main memory locations, and from memory to the I/O
subsystem
• Supports PCI Express traffic class to allow external prioritization of traffic
• Supports transfers only between two Physical Addresses
— 32 bit (4 GB) addressing range on the Local System Memory Interface
— 32 bit addressing range on the Memory Mapped I/O Subsystem Interface
• Maximum transfer of 16 Mbyte transfers per block
• Fully programmable by the host CPU
— Configuration space mapping for DMA engine capability and control
— Memory-mapped space for DMA channel-specific register sets
• Chain mode DMA transfer with automatic data chaining for scattering/gathering of
data blocks
— DMA chaining continued until a “null” Descriptor Pointer is encountered
— Support for appending a block to the end of current DMA chain
— Automated descriptor retrieval from DDR during chaining – single read
• Programmable independent alignment between source and destination
— Byte aligned transfer on the DDR Memory Interface
— Byte aligned transfer on the I/O Subsystem Interface
• Support for non-coherent transfers both to and from system memory on a per
descriptor basis
— Independent control of coherency for source and destination
• Programmable support for interrupt generation on block–by-block basis
— Selectable MSI or legacy level-sensitive interrupt function
— End of current block transfer
— End of current chain
— For any error causing a transfer to abort
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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