EP80579 Datasheet, PDF (1204/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
between Start and Stop Frames. This mode of operation allows the SIW_SERIRQ to
be Idle when there are no IRQ/Data transitions which should be most of the time.
Once a Start Frame has been initiated the Host Controller takes over driving the
SIW_SERIRQ low in the next clock and continues driving the SIW_SERIRQ low for a
programmable period of three to seven clocks. This makes a total low pulse width
of four to eight clocks. Finally, the Host Controller drives the SIW_SERIRQ back
high for one clock, then tri-state.
Any SIW_SERIRQ Device (i.e., The SIU and WDT) which detects any transition on
an IRQ/Data line for which it is responsible must initiate a Start Frame in order to
update the Host Controller unless the SIW_SERIRQ is already in an SIW_SERIRQ
Cycle and the IRQ/Data transition can be delivered in that SIW_SERIRQ Cycle.
2. Continuous (Idle) Mode: Only the Host controller can initiate a Start Frame to
update IRQ/ Data line information. All other SIW_SERIRQ agents become passive
and may not initiate a Start Frame. SIW_SERIRQ is driven low for four to eight
clocks by Host Controller. This mode has two functions. It can be used to stop or
idle the SIW_SERIRQ or the Host Controller can operate SIW_SERIRQ in a
continuous mode by initiating a Start Frame at the end of every Stop Frame.
An SIW_SERIRQ mode transition can only occur during the Stop Frame. Upon
reset, SIW_SERIRQ bus is defaulted to Continuous mode, therefore only the Host
controller can initiate the first Start Frame. Slaves must continuously sample the
Stop Frames pulse width to determine the next SIW_SERIRQ Cycle’s mode.
33.7.1.2
SIW_SERIRQ Data Frame
Once a Start Frame has been initiated, the SIW watches for the rising edge of the Start
Pulse and start counting IRQ/Data Frames from there. Each IRQ/Data Frame is three
clocks: Sample phase, Recovery phase, and Turn-around phase. During the Sample
phase the SIW drives the SIW_SERIRQ low, if and only if, its last detected IRQ/Data
value was low. If its detected IRQ/Data value is high, SIW_SERIRQ is left tri-stated.
During the Recovery phase the SIW drives the SIW_SERIRQ high, if and only if, it had
driven the SIW_SERIRQ low during the previous Sample Phase. During the Turn-around
Phase the SIW tri-states the SIU_SERIRQ. The SIW drives the SIW_SERIRQ line low at
the appropriate sample point if its associated IRQ/Data line is low, regardless of which
device initiated the Start Frame.
The Sample Phase for each IRQ/Data follows the low to high transition of the Start
Frame pulse by a number of clocks equal to the IRQ/Data Frame times three, minus
one. (e.g., The IRQ5 Sample clock is the sixth IRQ/Data Frame, (6 x 3) - 1 = 17th clock
after the rising edge of the Start Pulse).
Table 33-37. SIW_SERIRQ Sampling Periods (Sheet 1 of 2)
SIW_SERIRQ PERIOD
1
2
3
4
5
6
7
8
9
10
11
SIGNAL SAMPLED
Not Used
IRQ1
IRQ2
IRQ3
IRQ4
IRQ5
IRQ6
IRQ7
IRQ8
IRQ9
IRQ10
# OF CLOCKS PAST START
2
5
8
11
14
17
20
23
26
29
32
Intel^® EP80579 Integrated Processor Product Line Datasheet
1204
August 2009
Order Number: 320066-003US