EP80579 Datasheet, PDF (1247/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
35.6.1.11 Offset 14h: IOBAR – CSR I/O Mapped BAR Register
The IOBAR is a PCI BAR in I/O space that allows access to the Gigabit MAC structures
through IA I/O space. See Section 35.7, “Gigabit Ethernet MAC I/O Spaces: Bus M,
Device 0-2, Function 0” on page 1261 for a description of the individual registers this
region exposes.
Table 35-16. Offset 14h: IOBAR: CSR I/O Mapped BAR Register
Description:
View: PCI 1
BAR: Configuration
Bus:Device:Function: M:0:0
Offset Start: 14h
Offset End: 17h
View: PCI 2
BAR: Configuration
Bus:Device:Function: M:1:0
Offset Start: 14h
Offset End: 17h
View: PCI 3
BAR: Configuration
Bus:Device:Function: M:2:0
Offset Start: 14h
Offset End: 17h
Size: 32 bit
Default: 00000001h
Power Well: Core
Bit Range
31 : 05
04 : 02
01
00
Bit Acronym
Bit Description
Sticky
ADDR
ZERO
Reserved
TYP
Upper Programmable Base Address: These bits are set
by BIOS to locate the base address of the region.
Lower Bits: Hardwired to 0 to set the region size to 32B.
Reserved
Addressing Type: Hardwired to 1 to identify the region as
in I/O space.
Bit Reset
Value
0h
0h
0h
1
Bit Access
RW
RO
RO
RO
Reads and writes to addresses mapped through this BAR are redirected to structures
exposed through the CSRBAR (see Section 35.6.1.10, “Offset 10h: CSRBAR – Control
and Status Registers Base Address Register” on page 1246).
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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