EP80579 Datasheet, PDF (337/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
12.10
Note:
• Destination Coherency: specifies whether destination addresses should be snooped
on the FSB
• Source Coherency: specifies whether source addresses should be snooped on the
FSB
• Destination Type: specifies whether the destination is local memory or the I/O
subsystem
• Source Type: specifies whether the source is local memory or the I/O subsystem
(defined only for symmetry, I/O subsystem source addresses are not supported)
• Abort Interrupt Enable: specifies whether to generate an interrupt on abort
• Stop Interrupt Enable: specifies whether to generate an interrupt on stop
• Suspend Interrupt Enable: specifies whether to generate an interrupt on suspend
• End of Transfer Interrupt Enable: specifies whether to generate an interrupt on EOT
• End of Chain Interrupt Enable: specifies whether to generate an interrupt on EOC
Refer to Chapter , “Offset 2Ch: DCR0 - Channel 0 Descriptor Control Register,” for the
format of the DCR.
Interrupts
Each EDMA channel can be configured to generate interrupts to the processor interface.
The interrupt enable bits for end of transfer and end of chain in the Descriptor Control
Register (DCR) determine if the channel generates an interrupt upon successful error-
free completion of a transfer. The Abort Interrupt Enable bit in the DCR determines if
the channel generates an interrupt upon encountering an error. Refer to “Error
Conditions” on page 329 for details on errors on both the source and destination
interface. Table 12-2 summarizes the status flags, and the conditions under which
interrupts will be generated.
Each chain descriptor can independently set or clear the various interrupt enable bits in
the Descriptor Control Register. This level of control for interrupt generation permits
flexibility in synchronization between application software and transfers in progress. If
interrupts are not enabled, synchronization can be achieved by polling the status bits in
the Channel Status Register (CSR).
“-” In the table below equates to a non valid combination
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
337