EP80579 Datasheet, PDF (397/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
16.1.1.11 Offset 2Eh: SID - Subsystem Identification Register
This value is used to identify a particular subsystem.
Table 16-12. Offset 2Eh: SID - Subsystem Identification Register
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:0:0
Offset Start: 2Eh
Offset End: 2Fh
Size: 16 bit
Default: 0000h
Power Well: Core
Bit Range
15 : 00
Bit Acronym
Bit Description
Sticky
SUBID
Subsystem ID: This field must be programmed during
BIOS initialization. After it has been written once it
becomes Read-Only. When any byte or combination of
bytes of this register is written, the register value locks and
cannot be further updated.
Bit Reset
Value
0000h
Bit Access
RWO
16.1.1.12 Offset 4Ch: NSIBAR - Root Complex Block Address Register
This is the base address for the Root Complex memory-mapped configuration space.
This window of addresses contains the Root Complex Register Block for the NSI
hierarchy associated with the IMCH. There is no physical memory within this 4 Kbyte
window that can be addressed. The 4 Kbyte reserved by this register does not alias to
any PCI 2.3 compliant memory mapped space.
All accesses to these Memory Mapped Registers must be made as a single Dword (4
bytes) or less. Access must be aligned on a natural boundary.
Table 16-14. Offset 4Ch: NSIBAR - Root Complex Block Address Register
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:0:0
Offset Start: 4Ch
Offset End: 4Fh
Size: 32 bit
Default: 00000000h
Power Well: Core
Bit Range
31 : 12
11 : 00
Bit Acronym
Bit Description
Sticky
NSI_BA
Reserved
NSI Base Address: The BIOS programs this register
resulting in a base address for a 4 Kbyte block of
contiguous memory address space. This register ensures
that a naturally aligned 4 Kbyte space is allocated within
total addressable memory space of 4 Gbyte.
System Software uses this base address to program the
NSI register set.
When IMCH TST2[5] = 1, the NSI Memory Mapped
Register space is visible and memory mapped accesses are
claimed and decoded appropriately.
When IMCH TST2[5] = 0, the NSI Memory Mapped
Register space is disabled and does not claim any memory.
(THE NSIBAR register is still read/write accessible.)
Hardwired to 0
Bit Reset
Value
00000h
000h
Bit Access
RW or RO
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
397