EP80579 Datasheet, PDF (1056/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
27.3.3.1 Offset 00h: PM1_STS – Power Management 1 Status Register
Table 27-11. Offset 00h: PM1_STS – Power Management 1 Status Register (Sheet 1 of 2)
Description:
View: PCI
Size: 16 bit
BAR: PMBASE (IO)
Default: 0000h
Bus:Device:Function: 0:31:0
Offset Start: 00h
Offset End: 00h
Power Well: Core^a
Bit Range
15
14
13 : 12
11
10
09
Bit Acronym
Bit Description
Sticky
WAK_STS
0 = Software clears this bit by writing a 1 to it.
1 = This bit can only be set by hardware when the
system is in one of the Sleep states (via the
SLP_EN bit) and an enabled Wake event occurs.
Upon setting this bit, CMI will transition the system
to the ON state.
This bit is not affected by hard resets caused by a CF9
write, but is reset by RSMRST#.
If a power failure occurs (such as removed batteries)
without the SLP_EN bit set, the WAK_STS bit will not be
set when the power returns if the AFTER_G3 bit is 0. If
the AFTER_G3 bit is 1, then the WAK_STS bit will be set
after waking from a power failure. If necessary, the
BIOS can clear the WAK_STS bit in this case.
Reserved Reserved.
Reserved Reserved
0 = Software clears this bit by writing a 1 to it.
1 = This bit is set any time a Power Button Override
Event occurs (i.e., the power button is pressed for
at least 4 consecutive seconds), or due to the
corresponding bit in the SMBus slave message, or
due to an internal thermal sensor catastrophic
PRBTNOR_STS
condition. These events cause an unconditional
transition to the S5 state, as well as sets the
AFTERG3 bit. The BIOS or SCI handler clears this
bit by writing a 1 to it. This bit is not affected by
hard resets via CF9h writes, and is not reset by
RSMRST#. Thus, this bit is preserved through
power failures.
RTC_STS
0 = Software clears this bit by writing a 1 to it.
1 = Set when the RTC generates an alarm (assertion of
the IRQ8# signal), and is not affected by any other
enable bit. See RTC_EN for the effect when
RTC_STS goes active.
This bit is only set by hardware and can only be reset by
writing a one to this bit position. This bit is not affected
by hard resets caused by a CF9 write, but is reset by
RSMRST#.
Additionally if the RTC_EN bit (PMBASE + 02h, bit 10) is
set, the setting of the RTC_STS bit will generate a wake
event.
Reserved Reserved
Bit Reset
Value
0h
0h
00h
0h
0h
0h
Bit Access
RWC
RWC
RWC
Intel^® EP80579 Integrated Processor Product Line Datasheet
1056
August 2009
Order Number: 320066-003US