EP80579 Datasheet, PDF (1525/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
37.6.6.37 RJC – Receive Jabber Count Register
This register counts the number of received frames that passed address filtering, and
were greater than maximum size and had a bad CRC (this is slightly different from the
“ROC – Receive Oversize Count Register” on page 1524). Packets over 1522B are
oversized if LongPacketEnable is 0. If LongPacketEnable (LPE) is 1, then an incoming
packet is considered oversized if it exceeds 16384 bytes. If receives are not enabled,
this register will not increment. These lengths are based on bytes in the received
packet from <Destination Address> through <CRC>, inclusively.
Table 37-115.RJC: Receive Jabber Count Register
Description:
View: PCI 1
BAR: CSRBAR
Bus:Device:Function: M:0:0
Offset Start: 40B0h
Offset End: 40B3h
View: PCI 2
BAR: CSRBAR
Bus:Device:Function: M:1:0
Offset Start: 40B0h
Offset End: 40B3h
View: PCI 3
BAR: CSRBAR
Bus:Device:Function: M:2:0
Offset Start: 40B0h
Offset End: 40B3h
Size: 32 bits
Default: 00000000h
Power
Well:
GbE0: Aux
Gbe1/2: Core
Bit Range Bit Acronym
Bit Description
31 : 00
RJC
Number of receive jabber errors
Sticky
Bit Reset
Value
0h
Bit Access
RC
37.6.6.38 TORL – Total Octets Received Low Register
This is the low 32b of a register that counts the total number of octets received,
including octets from both good and bad packets. Packets must first pass the MAC
address filtering (Broadcast or Individual-Address/Multicast match) - packets not for
this MAC are not included. Octets will be counted for all packets regardless of their
length, whether they encountered errors, whether they are detected as regular packets
or flow control packets, and regardless of whether they are stored successfully versus
dropped from a Receive FIFO (Receive Packet Buffer). Bytes from the <Destination
Address> field through the <CRC> field (inclusively) are counted. {TORH,TORL}
together make up a logical 64-bit register. Each half must be accessed independently
using separate 32-bit accesses. Both registers are reset when the upper 32-bit value
(TORH) is read. The register sticks at 0xFFFF_FFFF_FFFF_FFFF.
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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