EP80579 Datasheet, PDF (1425/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
37.6
37.6.1
Note:
GbE Controller Register Summary
This section details the programmer-visible state inside the GbE controller. In some
cases, it describes hardware structures invisible to software in order to clarify a
concept.
The GbE address space is directly memory-mapped to 128 Kbyte of internal registers
and memories. This register and memory space is divided into the following categories:
• General
• Receive
• Transmit
• Statistics
• Diagnostics (including packet buffer memory access)
• The external PHY registers are accessed through the MDIO interface. (For more
information on MDIO, see “Global Configuration Unit”.)
Registers Overview
The Gigabit Ethernet Controller registers materialize in PCI space. For more information
on the conventions the following register summaries adopt, see Section 7.1, “Overview
of Register Descriptions and Summaries” on page 183.
The completion of any CSR access will be held off (maximum estimated delay 5ms) if
initiated prior to completion of HW initialization (e.g.-EEPROM read). This behavior is
transparent to software.
Table 37-21, Table 37-22, and Table 37-23 summarize the Gigabit Ethernet interface
#0, #1, and #2 materializations from the PCI perspective.
Table 37-21. Bus M, Device 0, Function 0: Summary of Gigabit Ethernet Interface Registers
Mapped Through CSRBAR Memory BAR (Sheet 1 of 4)
Offset Start Offset End
Register ID - Description
0000h
0008h
0018h
00E0h
0010h
0014h
0028h
002Ch
0030h
0038h
0170h
1000h
00C0h
00C4h
00C8h
0003h
000Bh
001Bh
00E3h
0013h
0017h
002Bh
002Fh
0033h
003Bh
0173h
1003h
00C3h
00C7h
00CBh
“CTRL: Device Control Register” on page 1438
“STATUS: Device Status Register” on page 1441
“CTRL_EXT: Extended Device Control Register” on page 1442
“CTRL_AUX: Auxiliary Device Control Register” on page 1444
“EEPROM_CTRL - EEPROM Control Register” on page 1446
“EEPROM_RR – EEPROM Read Register” on page 1448
“FCAL: Flow Control Address Low Register” on page 1449
“FCAH: Flow Control Address High Register” on page 1450
“FCT: Flow Control Type Register” on page 1451
“VET: VLAN EtherType Register” on page 1452
“FCTTV: Flow Control Transmit Timer Value Register” on page 1452
“PBA: Packet Buffer Allocation Register” on page 1453
“ICR0: Interrupt 0 Cause Read Register” on page 1454
“ITR0: Interrupt 0 Throttling Register” on page 1457
“ICS0: Interrupt 0 Cause Set Register” on page 1458
Default
Value
00000A09h
0000XXXXh
00000000h
00000100h
00000X1Xh
XXXXXX00h
00c28001h
00000100h
00008808h
00008100h
00000000h
00100030h
00000000h
00000000h
00000000h
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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