EP80579 Datasheet, PDF (129/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 3-12. PCI Configuration Header Support for Type 1 Headers in AIOC Devices (Sheet
3 of 3)
Offset Register and Field Bit(s) Supt.^a Acc.^b
Notes
3Eh - 3Fh
Discard Timer
SERR# Enable
11
Discard Timer
Status
10
Secondary Discard
Timeout
9
Primary Discard
Timeout
8
Fast Back-to-Back
Enable
7
Secondary Bus
Reset
6
Master Abort Mode 5
VGA Enable
3
ISA Enable
2
SERR# Enable
1
Parity Error
Response
0
N
RO Not supported.
N
RO Not supported.
N
RO Not supported.
N
RO Not supported.
N
RO Not supported.
N
RW Not supported.
Y
RO
Bridge delivers events that would be master
aborts (primarily address decode) as SERR#.
N
RW Not supported.
N
RW Not supported.
N
RW Not supported.
N
RW Not supported.
a. Supported fields provide appropriate PCI semantics. Unsupported fields always return zero on reads unless
otherwise noted and need not provide PCI semantics.
b. RO and RW access types indicate that the register or field supports read-only access and read/write access,
respectively.
c. This is a known deviation from the PCI specification since the bridge can be a bus master.
d. This is a deviation from the PCI specification since this register should be RO on bridges that do not support
prefetchable regions. The registers are RW for compatibility with the base IP. Software is expected to set these
fields to indicate an empty region since no secondary-side devices (i.e., bus M) request prefethcable memory.
For additional details on the headers for AIOC devices, see Section 35.3.1, “Description
of PCI Configuration Header Space”.
The specific portion of the 256B PCI configuration space that is active in a device
depends on the needs of the specific device. In general, a device requires far less than
256B of storage to implement a typical configuration space. Regions of the 256B
configuration space that are not required are reserved and need only support default
behavior compliant with the PCI specification:
All PCI devices must treat Configuration Space write operations to reserved
registers as no-ops; that is, the access must be completed normally on the bus and
the data discarded. Read accesses to reserved or unimplemented registers must be
completed normally and a data value of 0 returned.
§§
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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