EP80579 Datasheet, PDF (1889/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 49-80. MDIO Timings Values
Symbol
Parameter
t₁
MDIO, clock to output timing with respect
to rising edge of MDC clock
t₂
MDIO output hold timing after the rising
edge of MDC clock
t₃
MDIO input setup prior to rising edge of
MDC clock
t₄
MDIO input hold time after the rising
edge of MDC clock
t5
MDC clock period
Notes:
1.
The MDC clock period is 641 ns in SKU 2 and 8
Min
10
10
0
-
Max
MDC/2 + 10
ns
Units
ns
ns
Figure
49-40
49-40
Notes
-
-
ns
49-41
-
-
ns
49-41
-
500
ns
49-41
1
49.5.13.3.9 EEPROM Timing Specification
This section describes the AC timing for the EEPROM interface.
Figure 49-42 shows a typical EEPROM read operation generated by the EP80579.
Figure 49-42.EEPROM Interface Timing Diagram
EECS
EESK
EEDI
EEDO
1
tcs tck
3
tsu
21
th
4
1 0 A7 A6 A5 A4 A3 A2 A1 A1
7
tcsl
start _read opcode=10
56
D15 D14
D1
D
0
B6591-01
Table 49-81. EEPROM Read Operation (Sheet 1 of 2)
Step
1
2
3
4
Parameter
The EP80579 activates the EEPROM by asserting EECS.
After the chip select, The EP80579 starts driving data.
It drives a 1 for the start bit, then a 10 (binary) for the read opcode.
The EP80579 starts driving the clock after driving the initial start bit.
The EEPROM device latches a bit on every rising edge of the clock.
The output data is driven near the falling edge of the clock to maximize setup and hold times.
Likewise the read data is sampled near the falling edge of the clock.
After driving the start bit and read opcode EP80579 drives the address, starting at the most
significant bit. A 256-word EEPROM requires 8 address bits (as shown in the diagram), while a 64-
word EEPROM requires only 6 address bits.
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
1889