EP80579 Datasheet, PDF (666/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
16.6.1.16 Offset 4Ch: CDUAR1 - Channel 1 Current Descriptor Upper Address
Register
Table 16-312.Offset 4Ch: CDUAR1 - Channel 1 Current Descriptor Upper Address Register
Description:
View: PCI
BAR: EDMALBAR
Bus:Device:Function: 0:1:0
Offset Start: 4Ch
Offset End: 4Fh
Size: 32 bit
Default: 00000000h
Power Well: Core
Bit Range Bit Acronym
Bit Description
Sticky
Bit Reset
Value
The bit descriptions for this register are identical to those described for CDUAR0 in Section 16.6.1.4.
Bit Access
16.6.1.17 Offset 50h: SAR1 - Channel 1 Source Address Register
Table 16-313.Offset 50h: SAR1 - Channel 1 Source Address Register
Description:
View: PCI
BAR: EDMALBAR
Bus:Device:Function: 0:1:0
Offset Start: 50h
Offset End: 53h
Size: 32 bit
Default: 00000000h
Power Well: Core
Bit Range Bit Acronym
Bit Description
Sticky
The bit descriptions for this register are identical to those described for SAR0 in Section 16.6.1.5.
Bit Reset
Value
Bit Access
16.6.1.18 Offset 54h: SUAR1 - Channel 1 Source Upper Address Register
Table 16-314.Offset 54h: SUAR1 - Channel 1 Source Upper Address Register
Description:
View: PCI
BAR: EDMALBAR
Bus:Device:Function: 0:1:0
Offset Start: 54h
Offset End: 57h
Size: 32 bit
Default: 00000000h
Power Well: Core
Bit Range Bit Acronym
Bit Description
Sticky
Bit Reset
Value
The bit descriptions for this register are identical to those for SUAR0 described in Section 16.6.1.6.
Bit Access
Intel^® EP80579 Integrated Processor Product Line Datasheet
666
August 2009
Order Number: 320066-003US