EP80579 Datasheet, PDF (1127/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
30.2.3 Interrupt Handling
30.2.3.1
Generating Interrupts
The PIC interrupt sequence involves three bits, from the IRR, ISR, and IMR, for each
interrupt level. These bits are used to determine the interrupt vector returned and
status of any other pending interrupts. These bits are defined in Table 30-16.
Table 30-16. Interrupt Handling
Bits
IRR
ISR
IMR
Name
Interrupt Request Register
Interrupt Service Register
Interrupt Mask Register
Description
This bit is set on a low to high transition of the interrupt line in edge
mode, and by an active high level in level mode. This bit is set
whether or not the interrupt is masked. However, a masked interrupt
will not generate INTR.
This bit is set, and the corresponding IRR bit cleared, when an
interrupt acknowledge cycle is seen, and the vector returned is for
that interrupt.
Determines whether an interrupt is masked. Masked interrupts do not
generate INTR.
30.2.3.2
Acknowledging Interrupts
The processor generates an interrupt acknowledge cycle that is translated into an
Interrupt Acknowledge Special Cycle to the IICH. The PIC translates this cycle into two
internal INTA# pulses expected by the 8259 cores. The PIC uses the first internal
INTA# pulse to freeze the state of the interrupts for priority resolution. On the second
INTA# pulse, the master or slave sends the interrupt vector to the processor with the
acknowledged interrupt code. This code is based upon bits [07:03] of the
corresponding ICW2 register, combined with three bits representing the interrupt within
that controller.
Table 30-17. Content of Interrupt Vector Byte
Master, Slave Interrupt
IRQ7,15
IRQ6,14
IRQ5,13
IRQ4,12
IRQ3,11
IRQ2,10
IRQ1,9
IRQ0,8
Bits [07:03]
ICW2[07:03]
Bits [02:00]
111
110
101
100
011
010
001
000
30.2.3.3
Hardware/Software Interrupt Sequence
1. One or more of the Interrupt Request lines (IRQ) are raised high in edge mode, or
seen high in level mode, setting the corresponding IRR bit.
2. The PIC sends INTR active (high) to the processor if an asserted interrupt is not
masked.
3. The processor acknowledges the INTR and responds with an interrupt acknowledge
cycle.
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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