EP80579 Datasheet, PDF (717/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 18-5. Offset 04h: TSTS1 - TCO 1 Status Register (Sheet 2 of 3)
Description:
View: PCI
BAR: TCOBASE (IO)
Bus:Device:Function: 0:31:0
Offset Start: 04h
Offset End: 04h
Size: 16 bit
Default: 0000h
Power Well: Core
Bit Range
08
07
06 : 04
03
Bit Acronym
Bit Description
Sticky
BIOSWR_STS
0 = Software clears this bit by writing a 1 to it.
1 = The CMI sets this bit and generates and SMI# to
indicate an illegal attempt to write to the BIOS.
This occurs when either:
a) The BIOSWP bit is changed from 0 to 1 and the
BLD bit is also set, or
b) any write is attempted to the BIOS and the
BIOSWP bit is also set.
Note: On write cycles attempted to the 4 Mbyte lower
alias to the BIOS space, the BIOSWR_STS is
not set.
This bit is in the RTC well.
0 = Cleared by writing a 1 to the bit position or by
RTEST# going active.
1 = This bit is set when the Year byte (index offset 09h)
rolls over from 1999 to 2000. If the bit is already 1,
it remains 1.
When this bit is set, an SMI# is generated. However,
this is not a wake event (i.e., if the system is in a
sleeping state when the NEWCENTURY_STS bit is set,
the system does not wake up).
Note: The NEWCENTURY_STS is not valid when the
RTC battery is first installed (or if the RTC
battery does not provide sufficient power when
NEWCENTURY_
STS
the system is unplugged). Software can
determine that the RTC well was not
maintained by checking the RTC_PWR_STS bit
(D31:F0:A4, bit 2) or by other means (such as
doing a checksum on the RTC RAM array).
If the RTC power is determined to not have
been maintained, the BIOS must set the time
to a legal value and then clear the
NEWCENTURY_STS bit.
The NEWCENTURY_STS bit may take up to 3 RTC clocks
for the bit to be cleared when a 1 is written to the bit to
clear it. After writing a 1 to the NEWCENTURY_STS bit,
software must not exit the SMI handler until verifying
that the bit has actually been cleared. This ensures that
the SMI is not reentered.
Reserved Reserved
TIMEOUT
0 = Software clears this bit by writing a 1 to it.
1 = Set to indicate that the SMI was caused by the TCO
timer reaching 0.
Note: The SMI handler must clear this bit to prevent
an immediate reentry to the SMI handler.
Bit Reset
Value
0h
0h
0h
0h
Bit Access
RWC
RWC
RO
RWC
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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