EP80579 Datasheet, PDF (649/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
:
Table 16-295.Offset 298h: WDLL_MISC - DLL Miscellaneous Control
Description: WDLL_MISC- DLL Miscellaneous Control
View: PCI
BAR: SMRBASE
Bus:Device:Function: 0:0:0
Offset Start: 298h
Offset End: 29Bh
Size: 32 bit
Default: 00000000h
Power Well: Core
Bit Range
31 :25
24 :24
Bit Acronym
Bit Description
Reserved
WLCKDLY
Reserved
0: delay ECC/DQS[8]/DQS_L[8] only, clocks not delayed
1: delay ECC/DQS[8]/DQS_L[8] and CK[2:0]/CK_L[2:0]
(Normal setting for DDR2)
Sticky
N
Y
Bit Reset
Value
0000000b
0b
Bit Access
RO
RW
23 :23
Reserved Reserved
N
0b
RO
See Table 16-294 for DQ/DQS
Connectivity:
[22] CS, ODT, CKE
[21] CK[5:3], CK_L[5:3]
22 :16
WL_PHSEL_MO
DE
[20]
[19]
WL_CNTL[0]
WL_CNTL[1]
(DQ[15:0], DQS/DQS_L[1:0])
(DQ[31:16], DQS/DQS_L[3:2])
Y
0000000b
RW
[18] WL_CNTL[4] (ECC[7:0], DQS/DQS_L[8],CK[2:0],
CK_L[2:0])
[17] WL_CNTL[2] (DQ[47:32], DQS/DQS_L[5:4])
[16] WL_CNTL[3] (DQ[63:48], DQS/DQS_L[7:6])
15 :12
11 :8
7 :4
3 :3
2 :0
Reserved
Reserved
Delay select for CK[5:3] and CK_L[5:3]:
WL_CNTRL
0xxx: no delay
1001: delay 1/4 clk1x
1000: delay 1/2 clk1x
1011: delay 3/4 clk1x
1100: delay 1 clk1x
OthersReserved
Delay select for CS, ODT and CKE
WL_CNTRL_A
0xxx: no delay
1001: delay 1/4 clk1x
1000: delay 1/2 clk1x
1011: delay 3/4 clk1x
1100: delay 1 clk1x
OthersReserved
Reserved Reserved
Reserved to Intel
WL_CMD_DLY
Encoded additional delay for CS, CKE, ODT
Delay introduced = (~100ps * WL_CMD_DLY)
N
0000000b
RO
Y
0000b
RW
Y
0000b
RW
N
0b
RO
Y
000b
RW
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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