EP80579 Datasheet, PDF (1071/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 27-20. Offset 34h: SMI_STS - SMI Status Register (Sheet 1 of 3)
Description:
View: PCI
BAR: PMBASE (IO)
Bus:Device:Function: 0:31:0
Offset Start: 34h
Offset End: 34h
Size: 32 bit
Default: 00000000h
Power Well: Core
Bit Range
31 : 27
26
25 : 21
20
19
18
17
16
15
14
13
Bit Acronym
Bit Description
Sticky
Reserved Reserved
SPI_SMI_STS
This bit will be set when the SPI logic is requesting an
SMI#.
Reserved Reserved
Reserved Reserved.
Reserved Reserved
INTEL_
USB2_STS
This non-sticky read-only bit is a logical OR of each of
the SMI status bits in the Intel-Specific USB 2.0 SMI
Status Register ANDed with the corresponding enable
bits.
This bit will not be active if the enable bits are not set.
Writes to this bit will have no effect.
LEGACY_
USB2_STS
This non-sticky read-only bit is a logical OR of each of
the SMI status bits in the USB 2.0 Legacy Support
Register ANDed with the corresponding enable bits.
This bit will not be active if the enable bits are not set.
Writes to this bit will have no effect.
SMBUS_
SMI_STS
This bit is set to 1 to indicate that the SMI# was caused
by:
A. The SMBus Slave receiving a message that an SMI#
must be caused.
B. The SMBALERT# signal goes active and the
SMB_SMI_EN bit is set and the SMBALERT_DIS bit is
cleared.
C. The SMBus Slave receiving a HOST_NOTIFY message
and the HOST_NOTIFY_INTREN and the SMB_SMI_EN
bits are set.
D. The SMBus Slave receiving a “SMI in S0” message.
This bit is sticky. It is cleared by writing a 1 to this bit
position.
Note: This bit is set from the 64 KHz clock domain
used by the SMBus. Software must wait at least
15.63 µs (= 1/64 kHz) after the initial assertion
of this bit before clearing it.
SERIRQ_
SMI_STS
0 = SMI# not caused by SERIRQ decoder.
1 = Indicates the SMI# was caused by the SERIRQ
decoder.
Note: This bit is not sticky. Writes to this bit will have
no effect.
This bit will be set at the rate determined by the
PERIODIC_STS
PER_SMI_SEL bits. If the PERIODIC_EN bit is also set,
an SMI# is generated. This bit is cleared by writing a 1
to this bit position.
TCO_STS
0 = SMI not caused by TCO logic.
1 = Indicates SMI was caused by the TCO logic.
The reset value of this bit may be overwritten soon after
reset by the TCO counter. Hence, it is possible that a
read to this register after reset will yield a 1 in this field.
Note: Will not cause wake event. This bit is cleared by
writing a 1 to this bit position.
Bit Reset
Value
0h
0
0h
0h
0h
0h
0h
0h
0h
0h
0h
Bit Access
RO
RO
RO
RWC
RO
RWC
RWC
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
1071