EP80579 Datasheet, PDF (290/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
• Supports 8-bank devices.
— 1 Gb and 2 Gb DDR2 parts
• Supports unbuffered and registered DIMMs
• Supports discrete memory components soldered on the board
— supports 2 DQ loads similar to the double sided DIMM configuration.
• One 72b wide DRAM interface, 64b data + 8b ECC.
— The 64b data interface can optionally configured to be a 32b interface with 8b
ECC. The 32b option provides half the total bandwidth compared to the 64b
interface, and meets the requirements for systems that are cost sensitive and
want to populate small memory footprint soldered on the mother board.
• Supports burst-of-4 mode with a minimum access size of 32B for the 64b interface.
— On the 64b interface accesses longer than 32B are serviced as multiple burst-
of-4 transactions without closing the page.
— On the 32b interface, the controller supports burst-of-8 for a minimum access
size that is still 32B.
• Optional error protection using ECC bits and error code that supports SEC/DED
(single bit error correction/double bit error detection). Please see “Offset 7Ch: DRC
– DRAM Controller Mode Register” for details.
— On a single bit error, the memory controller corrects the error bit and writes
back the correct data value to DRAM, if enabled by software selection.
— Does not support DED (double-bit error detect) retries.
• Supports maximum of 4 GB DRAM capacity as shown in Table 11-2.
— One memory channel
• Support for demand scrub in hardware
— Refer to Section 16.1.1.45, “Offset 88h: SDRC – DDR SDRAM Secondary
Control Register” on page 439 for details.
• Support for background scrubbing in hardware.
— Programmable hardware scrub engine that allows background scrub at a wide
range of rates, including, but not limited to: up to 4 GB every hour, day, week,
or very fast rates, mainly used for validation purposes.
The memory controller supports the following transactions
• Simple read transactions.
— Supported lengths - 1-7B, 8B, 16B, 24B, 32B, 64B
— Read transactions smaller than 32B will result in a full 32B read on the interface
• Simple write transactions.
— Supported lengths - 8B, 16B, 24B, 32B, 64B
— Writes of lengths 8B, 16B and 24B will take the same time on the interface as a
32B write, the actual bytes that are written are specified by the DQ masks
— Writes of length 40B, 48B, 56B will be treated as a 32B write followed by an 8B,
16B or 24B write
— Writes that are smaller than 8B (i.e 1-7B) require a read-modify-write
operation and these will be supported upstream in the pipeline in other units.
The memory controller will not support read-modify-write operation.
• CSR reads and writes
Intel^® EP80579 Integrated Processor Product Line Datasheet
290
August 2009
Order Number: 320066-003US