EP80579 Datasheet, PDF (510/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 16-128.Offset 80h: EDMA_FERR - EDMA First Error Register (Sheet 2 of 2)
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:1:0
Offset Start: 80h
Offset End: 83h
Size: 32 bit
Default: 00000000h
Power Well: Core
Bit Range
Bit Acronym
Bit Description
Sticky
11
Channel_1_Destina
tion_Address_Error
The destination address does not comply with the
destination type or range for DMA channel 1. (NON-
FATAL)
Y
10
Reserved
Reserved
09
Channel_1_Parity_ Data parity Error in reading source data from system
Error
memory for DMA channel 1. (NON-FATAL)
Y
08
Channel_1_Write_E Received write to RO descriptor registers for DMA
rror
channel 1. (NON-FATAL)
Y
The descriptor pointer in the next descriptor address
07
Channel_0_NDAR_ register is of incorrect type or range for DMA channel 0.
Addressing_Error This includes above TOM, not in a memory range, and
Y
above available address space. (NON-FATAL)
06
Channel_0_NDAR_
Alignment_Error
The descriptor pointer in the next descriptor address
register is not aligned to an eight double-word boundary
for DMA channel 0. (NON-FATAL)
Y
05
Channel_0_Source The source address does not comply with the source
_Address_Error type or range for DMA channel 0. (NON-FATAL)
Y
04
Reserved
Reserved
03
Channel_0_Destina
tion_Address_Error
The destination address does not comply with the
destination type or range for DMA channel 0. (NON-
FATAL)
Y
02
Reserved
Reserved
01
Channel_0_Parity_ Data parity Error in reading source data from system
Error
memory for DMA channel 0. (NON-FATAL)
Y
00
Channel_0_Write_E Received write to RO descriptor registers for DMA
rror
channel 0. (NON-FATAL)
Y
Bit Reset
Value
0b
0b
0b
0b
0b
0b
0b
0b
0b
0b
0b
0b
Bit Access
RWC
RWC
RWC
RWC
RWC
RWC
RWC
RWC
RWC
16.3.1.17 Offset 84h: EDMA_NERR - EDMA Next Error Register
This register captures EDMA channel errors after the FERR register is locked. This
register accumulates all subsequent errors for the EDMA channels. See Table 16-129
for bit definitions.
Intel^® EP80579 Integrated Processor Product Line Datasheet
510
August 2009
Order Number: 320066-003US