EP80579 Datasheet, PDF (1502/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
37.6.5.11 TADV – Transmit Absolute Interrupt Delay Value Register
The Transmit Absolute Interrupt Delay Value Register (TADV) may be used to coalesce
transmit interrupts, however, it may be necessary to ensure that no completed
transmission remains unnoticed for too long an interval in order ensure timely release
of transmit buffers. This register may be used to ensure that a transmit interrupt
occurs at some predefined interval after a transmit is completed. Like the TIDV, the
absolute transmit timer only applies to transmit descriptor operations where interrupt-
based reporting is requested (RS set) and the use of the timer function is requested
(IDE is set).
Table 37-77. TADV: Transmit Absolute Interrupt Delay Value Register
Description:
View: PCI 1
BAR: CSRBAR
Bus:Device:Function: M:0:0
Offset Start: 382Ch
Offset End: 382Fh
View: PCI 2
BAR: CSRBAR
Bus:Device:Function: M:1:0
Offset Start: 382Ch
Offset End: 382Fh
View: PCI 3
BAR: CSRBAR
Bus:Device:Function: M:2:0
Offset Start: 382Ch
Offset End: 382Fh
Size: 32 bits
Default: 00000000h
GbE0: Core
Power Well: Gbe1/2:
Core
Bit Range Bit Acronym
Bit Description
31 : 16
Rsvd
Reserved
Interrupt Delay Value.
Timer increments are
RMII: 1.28 microseconds
RGMII: 1.024 microseconds.
Sticky
Bit Reset
Value
0h
Bit Access
RV
15 : 00
The transmit interrupt delay timer (TIDV) can be used to
coalesce transmit interrupts. However, it might be
necessary to ensure that no completed transmit remains
unnoticed for too long an interval in order ensure timely
release of transmit buffers. This register can be used to
ENSURE that a transmit interrupt occurs at some
predefined interval after a transmit is completed. Like the
delayed-transmit timer, the absolute transmit timer ONLY
applies to transmit descriptor operations where (a)
IDV
interrupt-based reporting is requested (RS set) and (b) the
use of the timer function is requested (IDE is set).
This feature operates by initiating a countdown timer upon
successfully transmitting the buffer. When the timer
expires, a transmit-complete interrupt (ICR.TXDW) is
generated. The occurrence of either an immediate (non-
scheduled) or delayed transmit timer (TIDV) expiration
interrupt halts the TADV timer and eliminates any spurious
second interrupts.
Setting the value to 0b disables the transmit absolute
delay function. If an immediate (nonscheduled) interrupt is
desired for any transmit descriptor, the descriptor IDE
should be set to 0b.
Note: This timer ONLY causes an interrupt. It does NOT
cause a writeback
0h
RW
Intel^® EP80579 Integrated Processor Product Line Datasheet
1502
August 2009
Order Number: 320066-003US