EP80579 Datasheet, PDF (330/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
12.7.1
Note:
12.7.2
generate a IA-32 core interrupt upon detection of an error. Beyond this mechanism,
errors detected and logged in the CSR may be escalated as described in the chapter on
RASUM and exception handling.
Refer to the EDMA access disposition tables in Chapter 10.0, “System Address Map,” for
an overview of defined ranges in the memory map and associated EDMA access
treatment.
Controller Interface Error
The following errors may be reported for any EDMA initiated access, regardless of
target interface:
• Illegal NDAR address
— The descriptor pointer in NDAR is not naturally eight Dword aligned
— The value in NDAR does not point to a valid memory location
• Illegal source address
— Address does not comply with the Source Type bit in the DCR
— Address out of range
• Illegal destination address
— Address does not comply with the Destination Type bit in the DCR
— Address out of range
— Accesses to any IICH address region via the NSI
• Data parity error (corrupt data) returned by memory read retrieving descriptor
information
All controller interface errors are fatal to the transfer in process and will result in
channel abort.
This includes data parity errors, since an error in reading a descriptor implies a corrupt
descriptor in main memory, and in this case, it is impossible for the channel to
determine precisely what part of the descriptor is damaged. The automatic abort upon
detection of a corrupt descriptor is necessary to prevent any further data corruption as
a result of its execution.
Memory Interface Error
The following errors may be reported for a EDMA initiated access (read or write) on the
local memory interface:
• Addressing error (source or destination)
— Physical EDMA address above REMAPLIMIT (see Section 10.6.1)
— Physical address not allocated to memory (including PAM destination mapping)
— Physical address specified an illegal memory destination (e.g., protected SMM
range)
• Data parity error in reading data from the EDMA Data Queue
• Data parity error (poisoned data) returned by memory read for payload data
There is no time-out mechanism associated with transfers. The EDMA channel assumes
that all reads to memory will eventually return, although they may return corrupt data,
and will wait indefinitely for an outstanding read.
Intel^® EP80579 Integrated Processor Product Line Datasheet
330
August 2009
Order Number: 320066-003US