EP80579 Datasheet, PDF (1367/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
A Checksum offset (TDESC.CSO) field indicates where to insert a TCP checksum if this
mode is enabled, relative to the start of the packet. A Checksum start (TDESC.CSS)
field indicates where to begin computing the checksum. Both CSO and CSS are in units
of bytes. These must both be in the range of data provided to the device in the
descriptor. This means for short packets which are padded by software, CSS and CSO
must be in the range of the unpadded data length, not the eventual padded length (64
bytes). Hardware will not add the 802.1Q EtherType or the VLAN field following the
802.1Q EtherType to the checksum. So for VLAN packets, software can compute the
values to back out only on the encapsulated packet rather than on the added fields.
Note:
Although the EP80579’s GbE can be programmed to calculate and insert TCP checksum
using the legacy descriptor format as described above, it is recommended that software
use the newer TCP/IP Context Transmit Descriptor Format. This newer descriptor
format allows the hardware to calculate both the IP and TCP checksums for outgoing
packets. Refer to “Transmit Checksum Off loading” on page 1379 for more information
about how the new descriptor format can be used to accomplish this task.
The CMD byte stores the applicable command and has the fields shown in Figure 37-18.
Figure 37-18.Transmit Command (TDESC.CMD) Layout
7
6
5
4
3
IDE
VLE
DEXT
RPS
RS
IDE: Interrupt Delay Enable
2
1
0
IC
IFCS
EOP
VLE: VLAN Packet Enable
DEXT: Descriptor Extension (0 for legacy mode)
RPS: Report Packet Sent
RS: Report Status
IC: Insert Checksum
IFCS: Insert FCS
EOP: End of Packet
EOP indicates the last descriptor making up the packet when asserted. One or many
descriptors can be used to form a packet. Hardware inserts a checksum at the offset
indicated by the CSO field if the Insert Checksum bit (IC) is set. Checksum calculations
are for the entire packet starting at the byte indicated by the CSS field. A value of 0
corresponds to the first byte in the packet. Hardware ignores IC, and CSO unless EOP is
set. CSS must be set in the first descriptor for a packet. In addition, IC is ignored if
CSO or CSS are out of range. This occurs if (CSS >= length) OR (CSO >= length - 1).
Software must compute an offsetting entry-to back out the bytes of the header that
should not be included in the TCP checksum-and store it in the position where the
hardware computed checksum is to be inserted.
TDESC.CMD.RS tells the hardware to report the status information. This is used by
software that does in-memory checks of the transmit descriptors to determine which
ones are done. For example, if software queues up 10 packets to transmit, it can set
the RS bit in the last descriptor of the last packet. If software maintains a list of
descriptors with the RS bit set, it can look at them to determine if all packets up to (and
including) the one with the RS bit set have been buffered in the output FIFO. This is
done by looking at the status byte and checking the Descriptor Done (DD) bit. If DD is
set, the descriptor has been processed. Refer to Figure 37-19 on page 1368 for the
layout of the status field.
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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