EP80579 Datasheet, PDF (355/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 13-3. Offset 0CF8h: CONFIG_ADDRESS: Configuration Address Register (Sheet 2 of
2)
Description:
View: IA F Base Address: 0000h (IO)
Offset Start: 0CF8h
Offset End: 0CF8h
Size: 32 bit
Default: 00000000h
Power Well: Core
Bit Range Bit Acronym
Bit Description
Sticky
15 :11
10 :08
07 :02
01 :00
Device_Number Selects one of the 32 possible devices per bus.
Function_Numb
er
Selects
one
of
eight
possible
functions
within
a
device.
This field selects one register within the particular Bus,
Register_Numb Device, and Function as specified by the other fields in the
er
Configuration Address Register. This field is mapped to
A[07:02] during NSI or PCI Express Configuration cycles.
Reserved Reserved
Bit Reset
Value
0h
0h
0h
0h
Bit Access
RW
RW
RW
13.6.0.2
Offset 0CFCh: CONFIG_DATA - Configuration Data Register
CONFIG_DATA is a 32-bit read/write window into configuration space. The portion of
configuration space that is referenced by CONFIG_DATA is determined by the contents
of CONFIG_ADDRESS.
Table 13-4. Offset 0CFCh: CONFIG_DATA: Configuration Data Register
Description:
View: IA F Base Address: 0000h (IO)
Offset Start: 0CFCh
Offset End: 0CFCh
Size: 32 bit
Default: 00000000h
Power Well: Core
Bit Range
31 :00
Bit Acronym
Bit Description
Sticky
CDW
Configuration Data Window. If bit 31 of
CONFIG_ADDRESS is one any I/O access to the
CONFIG_DATA register is mapped to configuration space
using the contents of CONFIG_ADDRESS.
Bit Reset
Value
0h
Bit Access
RW
13.7
IMCH Memory Mapped Registers
Certain DRAM compensation control, EDMA control/status registers, NSI control/status
and PCI Express will reside in memory mapped space instead of configuration space.
These memory mapped address regions are setup through base address registers and
capability pointers, which will reside in configuration address space. These registers are
documented in the configuration register chapter. These base address registers follow
the standard definition as found in the PCI Express Specification.
These memory mapped register regions must not be marked as WC (Write-Combining),
as all accesses to the registers within these regions are limited to Dword access, and
write-combining is not allowed. Further, these registers must not be accessed utilizing
IA-32 core operations with a data operand size greater than 32-bits, as such access is
strictly unsupported by the IMCH.
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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