EP80579 Datasheet, PDF (1076/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
27.4
SMI#/SCI Generation
Upon any SMI# event taking place, IICH will assert SMI# to the processor, which will
cause it to enter SMM space. SMI# remains active until the EOS bit is set. When the
EOS bit is set, SMI# will go inactive for a minimum of 4 PCICLK. If another SMI event
occurs, SMI# will be driven active again.
The SCI is a level-mode interrupt that is typically handled by an ACPI-aware operating
system. In non-APIC systems (which is the default), the SCI IRQ is routed to one of the
8259 interrupts (IRQ9, 10, or 11). The 8259 interrupt controller must be programmed
to level mode for that interrupt.
In systems using the APIC, the SCI can be routed to interrupts 9, 10, 11, 20, 21, 22, or
23. The interrupt polarity changes depending on whether it is on an interrupt shareable
with a PIRQ or not; see Section 27.3.1 for details. The interrupt will remain asserted
until all SCI sources are removed.
Table 27-24 shows which events can cause an SCI and Table 27-26 shows the causes of
an SMI#.
Note:
Some events can be programmed to cause either an SMI# or SCI. The usage of the
event for SCI (instead of SMI#) is typically associated with an ACPI-based system.
Table 27-24. Causes of SCI
Cause
Additional Enables (See Note 1)
Where
Reported
PME#
PME_EN = 1
PME_STS
Internal EHCI wake (PME_B0)
PME_B0_EN = 1
PME_B0_STS
Power Button Press
PWRBTN_EN = 1
PWRBTN_STS
RTC Alarm
RTC_EN = 1
RTC_STS
Ring Indicate
RI_EN = 1
RI_STS
USB #1 wakes
USB1_EN = 1
USB1_STS
PROCHOT# pin active
ACPI Timer overflow (2.34 seconds)
TMROF_EN = 1
TMROF_STS
Any GPI
GPI[x]_Route = 10, GPE0[x]_EN = 1
GPE0[x]_STS
TCO SCI Logic (see Table 27-25)
TCOSCI_EN = 1
TCOSCI_STS
BIOS_RLS written to 1
GBL_EN = 1
GBL_STS
Notes: Causes of SCI:
1.
SCI_EN must be 1 to enable SCI
2.
SCI can be routed to cause Interrupt 9:11 or 20:23 (20:23 only available in APIC mode)
Note:
There are various sources that cause the TCO SCI, shown in Table 27-25.
Table 27-25. Causes of TCO SCI
Cause
Message from IMCH
Additional Enables
None
Where Reported
IMCHSCI_STS
Intel^® EP80579 Integrated Processor Product Line Datasheet
1076
August 2009
Order Number: 320066-003US