EP80579 Datasheet, PDF (985/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
26.2.1.10 Offset 10h: MBAR - Memory Base Address Register
Table 26-12. Offset 10h: MBAR - Memory Base Address Register
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:29:7
Offset Start: 10h
Offset End: 13h
Size: 32 bit
Default: 00000000h
Power Well: Core
Bit Range
31 :10
09 :04
03
02 :01
00
Bit Acronym
Bit Description
Sticky
BA
Reserved
PREF
TPE
RTE
Base Address: Bits [31:10] correspond to memory
address signals [31:10], respectively. This gives 1 KByte
of relocatable memory space aligned to 1 KByte
boundaries.
Reserved
Prefetchable: This bit is hardwired to 0 indicating that
this range must not be prefetched.
Type: This field is hardwired to 0 indicating that this
range can be mapped anywhere within 32-bit address
space.
Resource Type Indicator: This bit is hardwired to 0
indicating that the base address field in this register maps
to memory space.
Bit Reset
Value
0h
0h
0h
00h
0h
Bit Access
RW
RO
RO
RO
26.2.1.11 Offset 2Ch: SSVID - USB 2.0 Subsystem Vendor ID Register
Table 26-13. Offset 2Ch: SSVID - USB 2.0 Subsystem Vendor ID Register
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:29:7
Offset Start: 2Ch
Offset End: 2Dh
Size: 16 bit
Default: XXXXh
Power Well: Core
Bit Range
15 :00
Bit Acronym
Bit Description
Sticky
SSVID
This register, in combination with the USB 2.0 Subsystem
ID register, enables the operating system to distinguish
each subsystem from the others. Writes to this register
are enabled when the WRT_RDONLY bit (offset 80h, bit 0)
is set to 1.
Bit Reset
Value
XXXXh
Bit Access
RW
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
985