EP80579 Datasheet, PDF (256/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

9.1
9.2
Intel^® EP80579 Integrated Processor
System Architecture
CMI implements numerous RASUM (Reliability, Availability, Serviceability, Usability and
Manageability) features on multiple interfaces.
The IMCH and IICH consist of:
• A Memory Controller.
• A four-channel, descriptor-chain-based Enhanced DMA (EDMA) controller.
• Several I/O devices such as USB, SATA, etc.
• One x8 PCI Express* interface, which may be split into a pair of independent x4 or
x1 PCI Express* interfaces.
Desired I/O Controller Hub (IICH) functions are integrated eliminating the requirement
for a legacy I/O bridge.
CMI also supports:
• Two USB 2.0/1.1 ports
• Two SATA ports Gen1/Gen2
• One LPC bus
• One SPI port
• Two UART port
• Two SMBus ports
For additional information see Section 11.3, “Configurations” on page 291.
PCI Express*
CMI provides one configurable x8 PCI Express interface with a maximum theoretical
bandwidth of 4 GByte/s (aggregate). The x8 PCI Express interface may alternatively be
configured as two independent x4 or x1 PCI Express interfaces.
CMI is a root-class component as defined in the PCI Express* Interface Specification,
Rev 1.0a. The PCI Express interfaces support connection of CMI to a variety of other
bridges compliant with the same revision of the PCI Express* Interface Specification,
Rev 1.0a. For example, the Intel^® 82571EB Gigabit Ethernet adaptor and the Intel PCI
Express I/O processor are directly supported on any of these PCI Express ports. Other
compatible PCI Express devices implement functionality such as graphics, hardware
RAID controllers and TCP/IP off-load engines. These devices are available from Intel
and/or third-party vendors.
As required by the interface specification, CMI will automatically negotiate for and train
a single lane (x1) link if an attached device on any logical port fails to establish a viable
x4 or x8 connection. This does not imply a capability for CMI to support more than two
independent PCI Express ports of any width simultaneously on the x8 port, nor does it
imply that the remaining three lanes of a potential x4 port are useful once the
associated link has been established for x1 operation. Similarly, CMI will automatically
negotiate for and train a single lane (x1) link if an attached device on any logical port
fails to establish a viable x4 connection.
External bridge devices such as PCI or PCI-X Gigabit Ethernet or RAID storage devices
are directly supported on the PCI Express ports. This does not preclude connection of
the IMCH to other bridges compliant with the same revision of the PCI Express
Interface Specification.
Intel^® EP80579 Integrated Processor Product Line Datasheet
256
August 2009
Order Number: 320066-003US