EP80579 Datasheet, PDF (564/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
16.4.1.51 Offset 76h: PEALNKSTS - PCI Express* Link Status Register
This register provides information about PCI Express* Link specific parameters.
Table 16-190.Offset 76h: PEALNKSTS - PCI Express Link Status Register (Sheet 1 of 2)
Description:
View: PCI 1
BAR: Configuration
Bus:Device:Function: 0:2:0
Offset Start: 76h
Offset End: 77h
View: PCI 2
BAR: Configuration
Bus:Device:Function: 0:3:0
Offset Start: 76h
Offset End: 77h
Size: 16 bit
Default: 1001h
Power Well: Core
Bit Range
15
Bit Acronym
Bit Description
Sticky
LABS
Link Autonomous Bandwidth Status – This bit is Set by
hardware to indicate that hardware has autonomously
changed Link speed or width, without the Port transitioning
through DL_Down status, for reasons other than to
attempt to correct unreliable Link operation.
Bit Reset
Value
0b
Bit Access
RW1C
This bit must be set if the Physical Layer reports a speed or
width change was initiated by the Downstream component
that was indicated as an autonomous change
Link Bandwidth Management Status – This bit is Set by
hardware to indicate that either of the following has
occurred without the Port transitioning through DL_Down
status:
A Link retraining has completed following a write of 1b to
the Retrain Link bit
Note: This bit is Set following any write of 1b to the Retrain
14
LBMS
Link bit, including when the Link is in the process of
retraining for some other reason.
0b
RW1C
Hardware has changed Link speed or width to attempt to
correct unreliable Link operation, either through an LTSSM
timeout or a higher level process
This bit must be set if the Physical Layer reports a speed or
width change was initiated by the Downstream component
that was not indicated as an autonomous change.
Data Link Layer Link Active – This bit indicates the
13
DLLLA
status of the Data Link Control and Management State
Machine. 1b = in DL_Active state
0b = not in DL_Active state
Slot Clock Configuration: This bit indicates that the
component uses the same physical reference clock that the
platform provides on the connector.The Read function is
only allowed after Software/BIOS initialized the bit..
12
SCC
0 = The component in the slot uses an independent
reference clock, irrespective of the presence of a
reference on the connector.
1 = The component in the slot uses the same physical
reference clock provided on the connector.
Link Training: This read-only bit indicates that Link
training is in progress (Physical Layer LTSSM in
Configuration or Recovery state); hardware clears this bit
11
LT
once Link Training is successfully trained to the L0 state.
0 = Cleared by hardware once link training is complete
1 = Set by hardware when link training is in progress
0b
RO
1b
RWO
0b
RO
Intel^® EP80579 Integrated Processor Product Line Datasheet
564
August 2009
Order Number: 320066-003US