EP80579 Datasheet, PDF (1347/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
37.4.3.2 Memory Initialization
The GbE’s internal memory must be initialized after the GbE unit has been powered-up,
to insure that no ECC or parity errors are generated from the random state of memory
after a power-up. If an ECC or parity error is encountered, a soft reset must be issued,
then the entire affected memory (that reported the error) must be re-initialized to
remove the error, so that it doesn’t re-occur.
After each power-up and soft reset, and after the memories have been initialized as
described below, software must clear the appropriate ECC disable bits described in
Section 37.6.8.3, “MEM_STS – Memory Error Status Register” on page 1546. Neither
ECC nor parity errors will be reported nor will the GbE error handling be enabled (as
described in Section 37.5.12, “Error Handling” on page 1418) until these bits have
been cleared out. These may be cleared immediately after a soft reset if the error
condition that resulted in the soft reset did not involve an ECC or parity error from one
of these memories.
37.4.3.2.1 Packet Buffer Memory
The Packet Buffer memory is initialized through write accesses to the PBM locations. A
single PBM access will initialize four locations within the Packet Buffer memory, using
address bits 15:4 of the PBM access to select the 128bit Packet Buffer Memory location.
Therefore, 4096 writes are required to initialize the 64KB of packet memory, writing
every four PBM locations (PBM(0), PBM(4), PBM(8), etc.).
37.4.3.2.2 Descriptor Tx and Rx Memory
The Descriptor Tx and Rx memories are each initialized through write accesses to the
TXDESCM and RXDESCM locations. A single DESCTX or DESCRX access will initialize
four locations within the Descriptor memory, using address bits 15:4 of the access to
select the 128bit Descriptor Memory location. Therefore, 64 writes are required to
initialize the 1KB of descriptor memory, writing every four DESC locations (DESCRX(0),
DESCRX(4), DESCRX(8), etc.).
37.4.3.2.3 Multicast Filter and Special Packets Memory
The Multicast and VLAN filter memories are each initialized through write accesses to
the MTA and VFTA locations as described in Section 37.6.4.14, “MTA[0-127] – 128
Multicast Table Array Registers” on page 1488 and Section 37.6.4.17, “VFTA[0-127] –
128 VLAN Filter Table Array Registers” on page 1490. Initialization will require 128
writes to initialize the 512B of descriptor memory, writing every MTA or VLAN filter
location.
37.4.3.2.4 Flexible Filter Memory
The Flexible Filter memories are each initialized through write accesses to the FFVT and
FFMT locations as described in Section 37.6.7.12, “FFVT[0-127] – Flexible Filter Value
Table Registers” on page 1543 and Section 37.6.7.11, “FFMT[0-127] – Flexible Filter
Mask Table Registers (0x9000 - 0x93F8; RW)” on page 1542.
Initialization will require 128 writes to initialize the 512B of descriptor memory, writing
every MTA or VLAN filter location. Initialization will require 256 writes to initialize the
memories, writing every one of the 128 FFMT and FFVT locations.
37.4.3.2.5 Statistics Memory
The Statistics memory provides no write access, but is initialized by the GbE
automatically after a power-up reset or software reset.
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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