EP80579 Datasheet, PDF (1440/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 37-25. CTRL: Device Control Register (Sheet 3 of 3)
Description:
View: PCI 1
BAR: CSRBAR
Bus:Device:Function: M:0:0
Offset Start: 0000h
Offset End: 0003h
View: PCI 2
BAR: CSRBAR
Bus:Device:Function: M:1:0
Offset Start: 0000h
Offset End: 0003h
View: PCI 3
BAR: CSRBAR
Bus:Device:Function: M:2:0
Offset Start: 0000h
Offset End: 0003h
Size: 32 bits
Default: 00000A09h
GbE0: Aux
Power Well: Gbe1/2:
Core
Bit Range
09 : 08
07
06
05
04
03
02
01
00
Bit Acronym
Bit Description
Sticky
SPEED
Reserved
SLU
Rsvd
Rsvd
Rsvd
Rsvd
Rsvd
FD
Speed selection.
These bits are written by software (assuming, after reading
the PHY registers through the MDIO interface) to set the
MAC speed configuration. See “Physical Layer Auto-
Negotiation & Link Setup Features” on page 1394 for
details.
• 00 => 10 Mbps
• 01 => 100 Mbps
• 10 => 1000 Mbps
• 11 => reserved
Note: These bits affect the MAC speed setting only if
CTRL_EXT.SPD_BYPS or CTRL.FRCSPD are used.
Reserved
Set Link Up.
SLU must be set to ‘1’ to enable the MAC. This bit may also
be initialized by the APME bit in the EEPROM Initialization
Control Word3, if an EEPROM is used.
Reserved. Must be set to 0.
Reserved
Reserved
Reserved
Reserved. Must write ‘0’ to this bit.
1=
Full Duplex. Controls the MAC duplex setting.
0 = Half Duplex
1 = Full Duplex
In half-duplex mode, EP80579’s GbE transmits carrier
extended packets and can receive both carrier extended
packets, and packets transmitted with bursting.
*Note that this bit is loaded from the EEPROM, if present
Bit Reset
Value
10b
0h
0h
0h
0h
1
0h
0h
1
Bit Access
RW
RV
RW
RW
RV
RW
RV
RW
RW
Intel^® EP80579 Integrated Processor Product Line Datasheet
1440
August 2009
Order Number: 320066-003US