EP80579 Datasheet, PDF (1040/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
26.13.2.4 Offset B0h: CONFIG - Configuration Register
Table 26-58. Offset B0h: CONFIG - Configuration Register
Description:
View: PCI
BAR: MBAR
Bus:Device:Function: 0:29:7
Offset Start: B0h
Offset End: B0h
Size: 32 bit
Default: 00007F01h
Power Well: Core
Bit Range Bit Acronym
Bit Description
Sticky
31 :15
14 :08
07 :04
03 :00
Reserved Reserved
USB_ADDRESS_
CNF
7-bit field that identifies the USB device address used by
the controller for all Token PID generation. This is a RW
field that is set to 7Fh after reset.
Reserved Reserved
USB_ENDPOINT
_CNF
This 4-bit field identifies the endpoint used by
controller for all Token PID generation. This is
that is set to 01h after reset.
the
a RW
field
Bit Reset
Value
0h
7Fh
0h
1h
Bit Access
RW
RW
26.13.3
USB 2.0 Based Debug Port Theory of Operation
There are two operational modes for the USB debug port:
1. Mode 1 is when the Enhanced USB Host Controller is in a disabled state from the
viewpoint of a standard EHCI driver (i.e., Host Controller’s Run/Stop bit is 0). In
Mode 1, the Debug Port controller is required to generate ‘keepalive’ packets less
than 2 milliseconds apart to keep the attached debug device from suspending. The
keepalive packet must be a standalone 32-bit SYNC field.
2. Mode 2 is when the host controller is running (i.e., Host controller’s Run/Stop# bit
is 1). In Mode 2, the normal transmission of SOF packets (or SYNC keepalives if the
port is functionally disabled) will keep the debug device from suspending.
26.13.3.1 Behavioral Rules
3. In both modes 1 and 2, the Debug Port controller must check for software
requested debug transactions at least every 125 microseconds. If the debug port is
enabled by the debug driver, and the standard host controller driver resets the USB
port, USB debug transactions are held off for the duration of the reset and until
after the first SOF is sent.
4. If the standard host controller driver suspends the USB port, then USB debug
transactions are held off for the duration of the suspend/resume sequence and until
after the first SOF is sent.
5. The ENABLED_CNT bit in the debug register space is independent of the similar
port control bit in the associated Port Status and Control register.
Table 26-59 shows the debug port behavior related to the state of bits in the debug
registers as well as bits in the associated Port Status and Control register.
Intel^® EP80579 Integrated Processor Product Line Datasheet
1040
August 2009
Order Number: 320066-003US