EP80579 Datasheet, PDF (1605/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
40.0 SSP Serial Port
40.1
40.2
40.3
40.3.1
40.3.2
Overview
The SSP (Synchronous Serial Port) is a full-duplex synchronous serial interface. The
SSP can connect to a variety of external analog-to-digital (A/D) converters, audio and
telecom codecs, and many other devices that use serial protocols for transferring data.
It supports National Microwire*, Texas Instruments* synchronous serial protocol (SSP),
and Motorola* serial peripheral interface (SPI) protocol.
The SSP operates in master mode (the attached peripheral functions as a slave), and
supports serial bit rates from 7.2 Kbps to 1.84 Mbps. Serial data formats may range
from 4 to 16 bits in length. Two on-chip register blocks function as independent FIFOs
for data, one for each direction. The buffers are 16 entries deep x 16 bits wide.
This section describes the signal definitions and operations of the SSP functional block.
Feature List
A list of features is presented below:
• Supports National Microwire format.
• Supports Texas Instruments Synchronous Serial Protocol (SSP).
• Supports Motorola Serial Peripheral Interface (SPI).
• Supports serial data rates from 7.2 Kbps to 1.84 Mbps.
• Provides 32 byte FIFOs for both receive and transmit data.
Theory of Operation
Endianness
The SSP uses only bits 15:0 of the internal data bus, the host must format the data into
the two least significant bytes of the 32 bit internal bus transfer. The two high order
bytes are ignored. The SSP unit is accessed only using dword accesses.
Error Handling
No error handling is defined for this unit beyond the functional receiver overrun status
bit (ROR) (see Section 40.4.3.7) in the SSP Status Register (see Section 40.4.3). This
error condition causes the unit’s interrupt to be asserted and is non-maskable.
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
1605