EP80579 Datasheet, PDF (664/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 16-308.Offset 2Ch: DCR0 - Channel 0 Descriptor Control Register (Sheet 2 of 2)
Description:
View: PCI
BAR: EDMALBAR
Bus:Device:Function: 0:1:0
Offset Start: 2Ch
Offset End: 2Fh
Size: 32 bit
Default: 00000000h
Power Well: Core
Bit Range
06
05
04
03
02
01
00
Bit Acronym
Bit Description
Sticky
SRCT
DSTT
DABRTIE
DSTPIE
DSUSIE
EOTIE
EOCIE
Source Type:
Hardwired to 0:
0 = Indicates the source address points to local system
memory.
1 = Indicates that the source address points to I/O
memory.
Although an I/O source type is not supported, this bit
will reflect the actual source type as written by
software. The IMCH flags an error if the source address
range is not valid, and ignores the value of this bit.
Destination Type:
0 = Destination Address points to local system memory
1 = Destination Address points to I/O space
An error is signaled by the IMCHif the Destination
Address type read from the descriptor does not match
this setting.
Aborted Interrupt Enable: Indicates whether or not
an interrupt is generated when the DMA Aborted
(DABRT) bit in the CSR is set.
0 = Disable
1 = Enable
Stopped Interrupt Enable: Indicates whether or not
an interrupt is generated when the DMA Stopped
(DSTP) bit in the CSR is set.
0 = Disable
1 = Enable
Suspended Interrupt Enable: Indicates whether or
not an interrupt is generated when the DMA Suspended
(DSUS) bit in the CSR is set.
0 = Disable
1 = Enable
End of Transfer Interrupt Enable: Indicates whether
or not an interrupt is generated when the End of
Transfer (EOT) bit in the CSR is set.
0 = Disable
1 = Enable
End of Chain Interrupt Enable: Indicates whether or
not an interrupt is generated when the End of Chain
(EOC) bit in the CSR is set.
0 = Disable
1 = Enable
Bit Reset
Value
0b
0b
0b
0b
0b
0b
0b
Bit Access
RO
RO
RO
RO
RO
RO
RO
Intel^® EP80579 Integrated Processor Product Line Datasheet
664
August 2009
Order Number: 320066-003US