EP80579 Datasheet, PDF (1499/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
37.6.5.9
TIDV – Transmit Interrupt Delay Value Register
This register is used to delay interrupt notification for transmit operations by coalescing
interrupts for multiple transmitted buffers. Delaying interrupt notification helps
maximize the amount of transmit buffers reclaimed by a single interrupt. This feature
only applies to transmit descriptor operations where interrupt-based reporting is
requested (RS set) and the use of the timer function is requested (IDE is set).
Table 37-75. TIDV: Transmit Interrupt Delay Value Register
Description:
View: PCI 1
BAR: CSRBAR
Bus:Device:Function: M:0:0
Offset Start: 3820h
Offset End: 3823h
View: PCI 2
BAR: CSRBAR
Bus:Device:Function: M:1:0
Offset Start: 3820h
Offset End: 3823h
View: PCI 3
BAR: CSRBAR
Bus:Device:Function: M:2:0
Offset Start: 3820h
Offset End: 3823h
Size: 32 bits
Default: 00000000h
GbE0: Core
Power Well: Gbe1/2:
Core
Bit Range Bit Acronym
Bit Description
31 : 16
Rsvd
Reserved
Interrupt Delay Value.
Timer increments are
RMII: 1.28 microseconds
RGMII: 1.024 microseconds.
Sticky
Bit Reset
Value
0h
Bit Access
RV
15 : 00
• This register is used to delay interrupt notification for
transmit operations by coalescing interrupts for
multiple transmitted buffers. Delaying interrupt
notification helps maximize the amount of transmit
buffers reclaimed by a single interrupt. This feature
only applies to transmit descriptor operations where
(a) interrupt-based reporting is requested (RS set) and
(b) the use of the timer function is requested (IDE is
set).
• This feature operates by initiating a countdown timer
upon successfully transmitting the buffer. If a
subsequent transmit delayed-interrupt is scheduled
before the timer expires, the timer is re-initialized to
IDV
the programmed value and re-starts its countdown.
When the timer expires, a transmit-complete interrupt
(ICR.TXDW) is generated.
• Hardware always loads the transmit interrupt counter
whenever it processes a descriptor with IDE set even if
it is already counting down due to a previous
descriptor.
• Setting the value to 0 is not allowed. If an immediate
(non-scheduled) interrupt is desired for any transmit
descriptor, the descriptor IDE should be set to 0.
• The occurrence of either an immediate (non-
scheduled) or absolute transmit timer interrupt will
halt the TIDV timer and eliminate any spurious second
interrupts.
• Transmit interrupts due to a Transmit Absolute Timer
(TADV) expiration or an immediate interrupt (RS =1,
IDE=0) will cancel a pending TIDV interrupt. The TIDV
countdown timer is reloaded but halted, though it may
be restarted by a processing a subsequent transmit
descriptor.
0h
RW
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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