EP80579 Datasheet, PDF (1327/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
35.12.1.14 Offset 3Dh: IRQP – Interrupt Pin Register
Table 35-164.Offset 3Dh: IRQP: Interrupt Pin Register
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: M:8:0
Offset Start: 3Dh
Offset End: 3Dh
Size: 8 bit
Default: 01h
Power Well: Core
Bit Range
07 : 00
Bit Acronym
Bit Description
IRQP
Interrupt Pin: Set to 01h to indicate the device always
uses INTA# as its interrupt pin.
Sticky
Bit Reset
Value
01h
Bit Access
RO
35.12.1.15 Offset 40h: LEBCTL – LEB Control Register
Table 35-165.Offset 40h: LEBCTL: LEB Control Register
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: M:8:0
Offset Start: 40h
Offset End: 43h
Size: 32 bit
Default: 00h
Power Well: Core
Bit Range Bit Acronym
Bit Description
31 : 01
00
RSV
BSEN
Reserved
Byte Swap Control for LEB Controller.
‘0’ -> Byte swap not enabled
‘1’ -> Byte swap enabled.
Sticky
Bit Reset
Value
0
Bit Access
RO
0
RW
35.12.1.16 Offset DCh: PCID – Power Management Capability ID Register
The Power Management Capability record controls power management in the device. It
is a 6B PCI SIG-defined capability record and includes the PCID, PCP, PMCAP, and PMCS
fields of the configuration header.
For an overview of the power management capability of AIOC devices, see Section
35.5, “Power Management of AIOC Devices”.
Table 35-166.Offset DCh: PCID: Power Management Capability ID Register
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: M:8:0
Offset Start: DCh
Offset End: DCh
Size: 8 bit
Default: 01h
Power Well: Core
Bit Range Bit Acronym
Bit Description
07 : 00
PCID
Capability ID: PCI SIG assigned capability record ID
(01h, power management capability)
Sticky
Bit Reset
Value
Bit Access
01h
RO
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
1327