EP80579 Datasheet, PDF (1397/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

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Using values lower than a certain minimum (determined by the ratio of GTX/MTX_CLK
clock to link speed), will have no effect on back-to-back transmission. This is because
the device will not start transmission until the minimum IEEE IFS (9.6 us at 10Mb, 960
ns at 100 b, and 96 ns at 1 Gb) has been met regardless of the value of Adaptive IFS.
For example, if the GbE is configured for 100 Mbps operation, the minimum IEEE IFS at
100 Mbps is 960 nanoseconds. Setting AIFS to a value of 10 (decimal) would not effect
back-to-back transmission time on the wire, because the 800 ns delay introduced (10 *
80n s = 800 ns) is less than the minimum IEEE IFS delay of 960 ns. However, setting
this register with a value of 20, which corresponds to 1600 ns for the above example,
would delay back-to-back transmits because the ensuing 1600 ns delay is greater than
the minimum IFS time of 960 ns.
It is important to note that this register has no effect on transmissions that occur
immediately after receives, or on transmissions that are not back-to-back (unlike the
TIPG.IPGR1 and TIPG.IPGR2 settings -- see “TIPG – Transmit IPG Register” on
page 1493). In addition, Adaptive IFS also has no effect on re-transmission timing (re-
transmissions occur after collisions). Therefore, AIT.AIFS is only enabled in back-to-
back transmission.
Note:
The AIT.AIFS value is not additive to the TIPG.IPGT value; instead, the actual IPG
equals the larger of AIT.AIFS and TIPG.IPGT.
37.5.8.5
Flow Control
Flow control as defined in 802.3x, as well as the specific operation of asymmetrical flow
control defined by 802.3z, is supported in the MAC. The following six registers are
defined for the implementation of flow control:
The Flow Control Address High Register and the Flow Control Address Low
Register (FCAH and FCAL) - 6 byte flow control multicast address
Flow Control Type Register (FCT) - 16 bit field to indicate flow control type
Flow Control Receive Threshold High Register (FCRTH) - 13 bit high water
mark indicating receive buffer fullness
Flow Control Receive Threshold Low Register (FCRTL) - 13 bit low water
mark indicating receive buffer emptiness
Flow Control Transmit Timer Value Register (FCTTV) - 16 bit timer value to
include in transmitted PAUSE frame
Flow control is implemented as a means of reducing the possibility of receive buffer
overflows which result in the dropping of received packets, and allows for local
controlling of network congestion levels. This may be accomplished by sending an
indication to a transmitting station of a nearly-full receive buffer condition at a
receiving station.
The implementation of asymmetric flow control allows for one link partner to send flow
control packets while being allowed to ignore their reception; i.e. not required to
respond to PAUSE frames.
37.5.8.5.1 MAC Control Frames & Reception of Flow Control Packets
Three comparisons are used to determine the validity of a flow control frame:
• A match on the six byte multicast address for MAC Control Frames or to the station
address of the device (Receive Address Register 0).
• A match on the type field.
• A comparison of the MAC Control Opcode field.
The 802.3x standard defines the MAC Control Frame multicast address as 01-80-C2-
00-00-01. This address must be loaded into the Flow Control Address High Register and
the Flow Control Address Low Register (FCAH and FCAL).
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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