EP80579 Datasheet, PDF (558/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
16.4.1.46 Offset 6Ch: PEADEVCTL - PCI Express* Device Control Register
This register PCI Express* device specific parameters.
Table 16-185.Offset 6Ch: PEADEVCTL - PCI Express Device Control Register (Sheet 1 of 2)
Description:
View: PCI 1
BAR: Configuration
Bus:Device:Function: 0:2:0
Offset Start: 6Ch
Offset End: 6Dh
View: PCI 2
BAR: Configuration
Bus:Device:Function: 0:3:0
Offset Start: 6Ch
Offset End: 6Dh
Size: 16 bit
Default: 0000h
Power Well: Core
Bit Range
15
14 : 12
Bit Acronym
Bit Description
Sticky
Reserved
MRRS
Reserved
Max Read Request Size: This field sets maximum read
request size for the device as a requester. The IMCH does
not generate read requests with size exceeding the set
value. Defined encodings for this field are:
Note: 000b=128 B100b=2 Kbyte
001b=256 B101b=4 Kbyte
010b=512 B110b=Reserved
011b=1 Kbyte111b=Reserved
Bit Reset
Value
0b
000b
Bit Access
RW
11
10
09
08
07 : 05
04
ENS
AUXPPE
PFE
ETFE
MAXPS
ERO
Enable No Snoop: Permits the device to set the No Snoop
bit in the Requester Attributes of transactions that do not
require hardware enforced cache coherency. Even when
this bit is set, the device can only set the No Snoop
attribute on a transaction when the address of the
transaction is not stored on any cache in the system.
0 = Disable
1 = Enable
Software override on usage of the “No Snoop” attribute.
The IMCH hard-wires this bit to 0, as it never issues
transactions with that attribute set.
Auxiliary (AUX) Power PM Enable: Not Applicable.
Phantom Functions Enable: Not Applicable.
Extended Tag Field Enable: Not Applicable
Max Payload Size: This field sets maximum TLP payload
size for the device. As a receiver, the device must handle
TLPs as large as the set value; as transmitter, the device
must not generate TLPs exceeding the set value.
Permissible values that can be programmed are indicated
by the max_payload_size supported in the device
capabilities register.
Note: Encodings above 256B are not supported. RW
functionality is only maintained for compliance
testing of all register bits.
Defined encodings for this field are:
000b = 128 B
001b = 256 B
010b = 512 B
100b = 2 KByte
101b = 4 KByte
110b = Reserved
011b = 1 KByte
111b = Reserved
Enable Relaxed Ordering: If this bit is set the device is
permitted to set the Relaxed Ordering bit in the attributes
field of transactions it issues that do not require strong
write ordering. Hard-wired to “0” in the IMCH, as no such
transaction attributes are ever used on outbound requests.
0 = Disable
1 = Enable
0b
RO
0b
RO
0b
RO
0b
RO
000b
RW
0b
RO
Intel^® EP80579 Integrated Processor Product Line Datasheet
558
August 2009
Order Number: 320066-003US