EP80579 Datasheet, PDF (295/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 11-10. 1Gb Addressing
Configuration
Row Address
Column Address
Page Size
DDR2
128 Mb x 8
A0-A13
A0-A9
1KB
Table 11-11. 2Gb Addressing
Configuration
# of Banks
Bank Address
Auto Precharge
Row Address
Column Address
Page Size
DDR2
256 Mb x 8
8
BA0-BA2
A10
A0-A14
A0-A9
1KB
11.3.3 Memory Address Translation Tables
Section 11.3.3.1 shows the address bit translation from the system address to the
DRAM row/column/bank address for the different DDR2 configurations supported by
the memory controller.
256 Mb, 512 Mb, 1024 Mb and 2048 Mb DRAM device densities are shown but please
refer to Table 11-1 for supported DDR2 device densities and widths. The memory
capacity that can be achieved for each device density in the single and dual rank mode
is also shown in the address mapping tables.
11.3.3.1
DDR2 Address Translation Tables
Figure 11-1 shows the translation tables for 64 bit, burst size 4 devices in x8 width.
Note: only burst 4 is supported for a DDR2 64 data bit interface.
Figure 11-2 shows the translation tables for 32 bit, burst size 8 devices in x8 width.
Note: only burst 8 is supported for a DDR2 32 data bit interface.
For a list of memory controller supported DDR2 device types and widths see
Table 11-1.
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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