EP80579 Datasheet, PDF (421/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Note:
— Single DIMM with dual ranks should program DRB0 with the encoding for
memory capacity in row 0 and DRB2 with the encoding for memory capacity in
row 0 + row 1 + row 2. Further, DRB1 = DRB0 and DRB3 = DRB2.
• It must always be the case with the EP80579 memory controller that for single
rank, 1 DIMM systems, DRB0 = DRB1 = DRB2 = DRB3 and for all other
configurations, DRB0 = DRB1 < DRB2 = DRB3.
Table 11-7, “Supported Rank Configurations in Single and Dual DIMM mode” on
page 293 shows the mapping of the chip selects in the different legal rank populations
on the EP80579.
DRB0=DRAM Row 0, DRB1=DRAM Row 1, etc.
Table 16-42. Offset 60h: DRB[0-3] - DRAM Row [3:0] Boundary Register
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:0:0
Offset Start: 60h at 1h
Offset End: 60h at 1h
Size: 8 bit
Default: ffh
Power Well: Core
Bit Range
07 :00
Bit Acronym
Bit Description
Sticky
DRAM Row Boundary Address: This 8 bit value defines
the upper address for each row of DRAM rows. This 8 bit
DRAM_RBA value is compared against a set of address lines to
N
determine the upper address limit of a particular row. This
field corresponds to bits 33:26of the system address.
Bit Reset
Value
ffh
Bit Access
RW
16.1.1.40 Offset 70h: DRA[0-1] – DRAM Row [0:1] Attribute Register
The DRAM Row Attribute register defines the DRAM technology. DRA is used to
calculate the address mapping for column and row addresses as a function of DRAM
technology specified in the DTYPE, DW and DIMMTECH fields.
• DRA0 describes characteristics of rows 0 (even) and 1 (odd).
• DRA1 describes characteristics of rows 2 (even) and 3 (odd).
• Due to the rules of the EP80579 DDR configuration, many fields of DRA0 and DRA1
are not meaningful (they exist only for backward compatibility). For most
configurations, the values in DRA0[DW_EVEN] and DRA0[DIMMTECH_EVEN] are
used. An exception is DRA1[DIMMTECH_EVEN] which is used to select the size of
the devices on the second DIMM of a two DIMM system. See Table 16-43 for
details.
• Bit fields that are not valid because the rank (or row) is not populated should not
be changed. For such fields the reset value should be the benign state.
• The controller determines which of rows are populated after decoding the DRB
registers. Please see Section 16.1.1.39, “Offset 60h: DRB[0-3] – DRAM Row [3:0]
Boundary Register” for more details.
Note:
All fields of the DRA[1:0] register need to be consistent or else unreliable operation will
occur. For example the value programmed in NC_ODD should be consistent with the
DIMMTECH_ODD field. The number of columns depends on the device technology.
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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