EP80579 Datasheet, PDF (1360/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
in memory and the head pointer is incremented by hardware. When the head pointer is
equal to the tail pointer, the queue is empty. Hardware stops storing packets in system
memory until software advances the tail pointer, making more receive buffers available.
The receive descriptor head and tail pointers reference 16-byte blocks of memory.
Shaded boxes in the figure represent descriptors that have stored incoming packets but
have not yet been recognized by software. Software can determine if a receive buffer is
valid by reading descriptors in memory. Any descriptor with a non-zero status byte has
been processed by the hardware, and is ready to be handled by the software.
Note:
The head pointer points to the next descriptor that will be written back. At the
completion of the descriptor write-back operation, this pointer is incremented by the
number of descriptors written back. Hardware “owns” all descriptors between the head
and tail. Any descriptor not in this range is owned by software.
The receive descriptor ring is described by the following registers:
The Receive Descriptor Base Address High Register and the Receive
Descriptor Base Address Low Register (RDBAH and RDBAL) - These registers
indicate the start of the descriptor ring buffer; this 64-bit address is aligned on a
16B boundary. Hardware ignores the lower 4 bits.
Receive Descriptor Length Register (RDLEN) - This register determines the
number of bytes allocated to the circular buffer. This value must be a multiple of
128. Since each descriptor is 16 bytes in length, the total number of receive
descriptors is always a multiple of 8.
Receive Descriptor Head Register (RDH) - This register holds a value that is an
offset from the base, and indicates the in-progress descriptor. There can be up to
64K descriptors in the circular buffer. Hardware maintains a shadow copy that
includes those descriptors completed but not yet stored in memory.
Receive Descriptor Tail Register (RDT) - This register holds a value that is an
offset from the base, and identifies the location beyond the last descriptor
hardware can process. This is the location where software writes the first new
descriptor.
If software statically allocates buffers, and uses memory read to check for completed
descriptors, it simply has to zero the status byte in the descriptor to make it ready for
reuse by hardware. This is not a hardware requirement (moving the hardware tail
pointer is), but is necessary for performing an in-memory scan.
37.5.5.7
Receive Interrupts
The following sections indicate the presence of new packets.
37.5.5.7.1
Receive Timer (ICR.RXT0) Due to Absolute Timer (RADV)
• When a packet is received the Absolute Timer starts counting down. When it
reaches 0 it generates an interrupt and resets itself. It is also reset if an interrupt is
generated due to the Packet Delay Timer expiration. The absolute timer is disabled
if RADV is 0. To use the Absolute Timer only the RDTR register must be set to an
equal or greater value than RADV.
37.5.5.7.2
Receive Timer (ICR.RXT0) Due to Packet Delay Timer (RDTR)
• When a packet is received the Packet Delay Timer starts counting down. Every time
an additional packet is received the Packet Delay Timer is reset to its starting value.
When it reaches 0 it generates an interrupt and resets itself. It is also reset if an
interrupt is generated due to the Absolute Timer expiration.
• When RDTR is 0 interrupts are immediate. If RADV is non-0, and RDTR is equal to
or higher than RADV then the Packet Delay Timer will never generate any
interrupts as the Absolute Timer will always generate them first.
Intel^® EP80579 Integrated Processor Product Line Datasheet
1360
August 2009
Order Number: 320066-003US