EP80579 Datasheet, PDF (581/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
16.4.1.67 Offset 124h: HDRLOG2 - Header Log DW 2 (3rd 32 bits) Register
The function of the Header Log registers is described in Section 16.4.1.65, “Offset
11Ch: HDRLOG0 - Header Log DW 0 (1st 32 bits) Register”. Header Log DW2 contains
the third 32 bits of the header. Byte 8 of the header is located in byte 3 of the Header
Log Register 2, byte 9 of the header is in byte 2 of the Header Log Register 2 and so
forth. These bits are sticky through reset.
Table 16-206.Offset 124h: HDRLOG2 - Header Log DW 2 (3rd 32 bits) Register
Description:
View: PCI 1
BAR: Configuration
Bus:Device:Function: 0:2:0
Offset Start: 124h
Offset End: 127h
View: PCI 2
BAR: Configuration
Bus:Device:Function: 0:3:0
Offset Start: 124h
Offset End: 127h
Size: 32 bit
Default: 00000000h
Power Well: Core
Bit Range
31 : 00
Bit Acronym
Bit Description
Sticky
Header Log 2 A masked error (respective bit set to ‘1’ in
mask register) is not logged in the Header Log Register,
HL2
does not update the First Error Pointer, and is not reported Y
to the PCI Express* Root Complex by an individual device.
These bits are sticky through system reset.
Bit Reset
Value
00000000h
Bit Access
RO
16.4.1.68 Offset 128h: HDRLOG3 - Header Log DW 3 (4th 32 bits) Register
The function of the Header Log registers is described in Section 16.4.1.65, “Offset
11Ch: HDRLOG0 - Header Log DW 0 (1st 32 bits) Register”. Header Log DW3 contains
the fourth 32 bits of the header. For 16-byte headers, byte 12 of the header is located
in byte 3 of the Header Log Register 3, byte 13 of the header is in byte 2 of the Header
Log Register 3 and so forth. For 12 byte headers, values in this register are undefined.
These bits are sticky through reset.
Table 16-207.Offset 128h: HDRLOG3 - Header Log DW 3 (4th 32 bits) Register
Description:
View: PCI 1
BAR: Configuration
Bus:Device:Function: 0:2:0
Offset Start: 128h
Offset End: 12Bh
View: PCI 2
BAR: Configuration
Bus:Device:Function: 0:3:0
Offset Start: 128h
Offset End: 12Bh
Size: 32 bit
Default: 00000000h
Power Well: Core
Bit Range
31 : 00
Bit Acronym
Bit Description
Sticky
Header Log 3 A masked error (respective bit set to ‘1’ in
mask register) is not logged in the Header Log Register,
HL3
does not update the First Error Pointer, and is not reported Y
to the PCI Express* Root Complex by an individual device.
These bits are sticky through system reset.
Bit Reset
Value
00000000h
Bit Access
RO
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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