EP80579 Datasheet, PDF (1074/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
27.3.3.12 Offset 3Ah: ALT_GPI_SMI_STS - Alternate GPI SMI Status Register
Table 27-22. Offset 3Ah: ALT_GPI_SMI_STS - Alternate GPI SMI Status Register
Description:
View: PCI
BAR: PMBASE (IO)
Bus:Device:Function: 0:31:0
Offset Start: 3Ah
Offset End: 3Ah
Size: 16 bit
Default: 0000h
Power Well: Resume
Bit Range
15 : 00
Bit Acronym
Bit Description
Sticky
ALT_GPI_
SMI_STS
These bits report the status of the corresponding GPIs.
1 = active, -0 = inactive. These bits are sticky. If the
following conditions are true, then an SMI# will be
generated and the ALT_GPI_SMI_STS bit set:
1. The corresponding bit in the ALT_GPI_SMI_EN
register is set
2. The corresponding GPI must be routed in the
GPI_ROUT register to cause an SMI.
3. The corresponding GPIO must be implemented.
All bits are in the resume well. Default for these bits are
dependent on the state of the GPI pins.
Bit Reset
Value
0000h
Bit Access
RWC
27.3.3.13 Offset 44h: DEVTRAP_STS - DEVTRAP_STS Register
Each bit indicates if an access has occurred to the corresponding devices trap range, or
for bits 6:9 if the corresponding PCI interrupt is active. Write 1 to the same bit position
to clear it. This register is used by APM power management software to see if there has
been system activity. The periodic SMI# timer indicates if it is the right time to read the
DEVTRAP_STS register (PMBASE + 44h).
Table 27-23. Offset 44h: DEVTRAP_STS - DEVTRAP_STS Register (Sheet 1 of 2)
Description:
View: PCI
BAR: PMBASE (IO)
Bus:Device:Function: 0:31:0
Offset Start: 44h
Offset End: 44h
Size: 16 bit
Default: 0000h
Power Well: Core
Bit Range
15 : 13
12
11 : 10
09
Bit Acronym
Bit Description
Sticky
Reserved Reserved
KBC (60/64h):
0 = Indicates that there has been no access to this
D12_TRP_STS
device’s I/O range.
1 = This device’s I/O range has been accessed. Clear
this bit by writing a 1 to the bit location.
Reserved Reserved
D9_TRP_STS
PIRQ[D or H]:
0 = The corresponding PCI interrupts have not been
active.
1 = At least one of the corresponding PCI interrupts
has been active. Clear this bit by writing a 1 to the
bit location.
Bit Reset
Value
0h
0h
0h
0h
Bit Access
RWC
RWC
Intel^® EP80579 Integrated Processor Product Line Datasheet
1074
August 2009
Order Number: 320066-003US