EP80579 Datasheet, PDF (512/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 16-129.Offset 84h: EDMA_NERR - EDMA Next Error Register (Sheet 2 of 2)
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:1:0
Offset Start: 84h
Offset End: 87h
Size: 32 bit
Default: 00000000h
Power Well: Core
Bit Range Bit Acronym
Bit Description
Sticky
11
Channel_1_Des
tination_Addres
s_Error
The destination address does not comply with the
destination type or range for DMA channel 1. (NON-FATAL)
Y
10
Reserved Reserved
09
Channel_1_Pari Data parity Error in reading source data from system
ty_Error memory for DMA channel 1. (NON-FATAL)
Y
08
Channel_1_Wri Received write to RO descriptor registers for DMA channel
te_Error 1. (NON-FATAL)
Y
07
Channel_0_ND
AR_Addressing
_Error
The descriptor pointer in the next descriptor address
register is of incorrect type or range for DMA channel 0.
This includes above TOM, not in a memory range, and
above available address space. (NON-FATAL)
Y
Channel_0_ND The descriptor pointer in the next descriptor address
06
AR_Alignment_ register is not aligned to an eight double-word boundary
Y
Error
for DMA channel 0. (NON-FATAL)
05
Channel_0_Sou
rce_Address_Er
ror
The source address does not
or range for DMA channel 0.
comply with the
(NON-FATAL)
source
type
Y
04
Reserved Reserved
03
Channel_0_Des
tination_Addres
s_Error
The destination address does not comply with the
destination type or range for DMA channel 0. (NON-FATAL)
Y
02
Reserved Reserved
01
Channel_0_Pari Data parity Error in reading source data from system
ty_Error memory for DMA channel 0. (NON-FATAL)
Y
00
Channel_0_Wri Received write to RO descriptor registers for DMA channel
te_Error 0. (NON-FATAL)
Y
Bit Reset
Value
0b
0b
0b
0b
0b
0b
0b
0b
0b
0b
0b
0b
Bit Access
RWC
RWC
RWC
RWC
RWC
RWC
RWC
RWC
RWC
16.3.1.18 Offset 88h: EDMA_EMASK - EDMA Error Mask Register
This register masks the unit errors from being recognized and therefore not logged at
the unit or global level and no interrupt/messages are generated. All channels are
expected to use the same reporting structure, so only one 8-bit register is
implemented.
Intel^® EP80579 Integrated Processor Product Line Datasheet
512
August 2009
Order Number: 320066-003US