EP80579 Datasheet, PDF (375/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
15.2.1.3.4 ADDR2 – Address Byte 2 Register
This register must be programmed with the Device Number and Function Number of
the desired configuration register if for a configuration type access, otherwise it must
be set to zero.
Table 15-7. ADDR2 – Address Byte 2 Register
Position
Configuration Register Mode Description
07:03
02:00
Device Number. Can only be devices on the IMCH.
Function Number.
Memory Mapped Mode Description
Zeros used for padding.
15.2.1.3.5 ADDR1 – Address Byte 1 Register
This register must be programmed with the upper address bits for the register with the
4K region. Whether it is a configuration or memory-map type of access, only the lower
bits are utilized, the upper four bits are ignored.
Table 15-8. ADDR1 – Address Byte 1 Register
Position
Description
07:04
03:00
Ignored.
Extended Register Number. Upper address bits for the 4 K region of register offset.
15.2.1.3.6 ADDR0 – Address Byte 0 Register
This register indicates the lower eight address bits for the register within the 4 K
region, regardless of whether it is a configuration or memory-map type of access.
Table 15-9. ADDR0 – Address Byte 0 Register
Position
07:00
Register Offset.
Description
15.2.1.3.7 DATA – Data Register
This field is used to receive the read data or to provide the write data associated with
the desired register.
At the completion of a read command, this field contains the data retrieved from the
selected register. All reads return an entire aligned Dword (32 bits) of data.
The appropriate number of byte(s) of this 32-bit logical register must be written with
the desired write data prior to issuing a write command. For a byte write only, bits 7:0
are used, for a Word write, only bits 15:0 are used, and for a Dword write, all 32 bits
are used.
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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