EP80579 Datasheet, PDF (1422/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
— Transmit Registers
— Statistics Registers
— Diagnostic Registers
Of these registers, RAH/RAL, MTA[127:0], VFTA[127:0], TDBAH/TDBAL, and
RDBAH/RDBAL registers have no default value. If the functions associated with the
registers are enabled they must be programmed by software. Once programmed,
their value is preserved through all resets as long as power is applied to the bE.
4. See explanation of “EEPROM Resets” above
5. The Wake Up Context is defined in the PCI Bus Power Management Interface
Specifications. If includes:
— PME_En bit of the Power Management Control/Status Register (PMCSR)
— PME_Status bit of the Power Management Control/Status Register (PMCSR)
— The shadow copies of these bits in the Wakeup Control Register are treated
identically.
Note:
In situations where the device is reset using CTRL.RST, the TX data lines will be forced
to all zeros. This will cause a substantial number of symbol errors to be detected by the
link partner.
37.5.13.1 Soft Reset
This section describes software considerations when using the Soft Reset.
A Soft Reset operation is invoked by software via the Device Control Register
(CTRL.RST). The internal hardware reset is delayed until the internal bus is observed to
be idle, in order to ensure that no hardware bus protocols are violated. For the next 5
msec, the GbE component is undergoing a low-level hardware reset and re-read of
EEPROM in order to re-establish HW defaults. During this time, the GbE will not
respond to accesses to the device for a duration of approximately 5 msec.
Note:
Software MUST NOT access the GbE device for a minimum of 5 msec after writing the
soft-reset bit. Failure to do so may result in a system hang condition. An explicit
software wait of 5 milliseconds is necessary to ensure that the device has completed its
reset and will respond again.
CTRL.RST self clears upon completion of the reset operation. While the above required
wait interval is necessary to ensure that the reset operation is complete, a read of the
Device Control Register may be done after the wait interval to confirm the completion
of the reset.
37.5.13.2 MAC Disable
This feature allows the MAC and the I/O pins to be put into a very low-power mode.
The intended usage of this feature is when the GbE will not be used in the system (no
PHY connected).
When the GbE is disabled, all internal clocks are disabled and the GbE is held in reset.
The device does not respond to internal bus transactions. Effectively, the unit becomes
invisible to the system.
37.5.14
Endianness
Bytes for a receive packet arrive in the order shown from left to right: DA0 DA1 DA2
DA3 DA4 DA5 SA0 SA1 and so on. If the data were to be written to memory in the
order of arrival with the first byte written to the lowest address and each subsequent
Intel^® EP80579 Integrated Processor Product Line Datasheet
1422
August 2009
Order Number: 320066-003US