EP80579 Datasheet, PDF (873/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
23.3.4.8 Offset 13Ch: PxSNTF[0-1] – Port [0-1] SNotification Register
Table 23-71. Offset 13Ch: PxSNTF[0-1] – Port [0-1] SNotification Register
Description:
View: PCI
BAR: ABAR
Bus:Device:Function: 0:31:2
Offset Start: 13Ch, 1BCh
Offset End: 13Fh, 1BFh
Size: 32 bit
Default: 00000000h
Power Well: Core
Bit Range
31 : 16
15 : 00
Bit Acronym
Bit Description
Sticky
Reserved
PMN_15_0
Reserved
PM Notify (PMN[15:0]): This field indicates whether a
particular device with the corresponding PM Port number
issued a Set Device Bits FIS to the host with the
Notification bit set.
PM Port 0h sets bit 0
…
PM Port Fh sets bit 15
Individual bits are cleared by software writing 1’s to the
corresponding bit positions.
Note that, while this field is reset to default on a HBA
Reset, it is not reset by COMRESET or SRST.
Bit Reset
Value
0h
0000h
Bit Access
RO
RWC
23.4
Overview
The SATA host controller contains two modes of operation – a legacy mode using I/O
space, and an AHCI mode using memory space. The memory space bit GHC.AE, set by
software, indicates to hardware that AHCI is being used. Software must not implement
code which mixes the use of legacy mode and AHCI mode.
23.5
Legacy Operation
In this mode of operation, software is performing I/O operations to the controller and
SATA devices. The SATA controller is using the shadow registers as described in the
SATA specification, and performing master/slave operation on the ports. The EP80579
does not support slave operations.
Software must program the DEV bit in the task file as its first operation before
programming the rest of the transfer or setting the bus master registers.
23.5.1 Transfer Examples
23.5.1.1
Register FIS Only
If software only wishes to send a command to the SATA device, and does not wish for
any ATAPI or data transfer to occur, it will perform PIO operations, setting up the
required fields for the command, and either writing to the command register (1F7h for
primary, 177h for secondary) or control register (3F6h for primary, 376h for
secondary).
Hardware will send the register FIS with the appropriate field set for command or
control block, and upon reception of the device-to-host register FIS indicating
command completion, will update the shadow block.
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
873