EP80579 Datasheet, PDF (1028/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
• CMI may assert the interrupts that are based on the interrupt threshold as soon as
the status for the last complete transaction in the interrupt interval has been
posted in the internal write buffers. The requirement in the EHCI Specification (that
the status is written to memory) is met internally, even though the write may not
be seen on the IMCH/IICH interface before the interrupt is asserted.
• Since CMI only supports the 1024-element Frame List size, the Frame List Rollover
interrupt occurs every 1024 milliseconds.
• CMI delivers interrupts using PIRQ#[A].
• CMI does not modify the CERR count on an Interrupt IN when the “Do Complete-
Split” execution criteria are not met.
• For complete-split transactions in the Periodic list, the “Missed Microframe” bit does
not get set on a control-structure-fetch that fails the late-start test. If subsequent
accesses to that control structure do not fail the late-start test, then the “Missed
Microframe” bit will get set and written back.
26.9.1
Aborts on USB 2.0-Initiated Memory Reads
If a read initiated by the EHC receives any status other than “Successful” in the
completion packet, the EHC treats it as a fatal host error. The following actions are
taken when this occurs:
• The Host System Error status bit is set
• The DMA engines are halted, the Run/Stop bit is cleared, and the HCHalted bit is
set, after completing up to one more transaction on the USB interface
• If enabled (by the Host System Error Enable), then an interrupt is generated
• If the status is Master Abort, then the Received Master Abort bit in configuration
space is set
• If the status is Target Abort, then the Received Target Abort bit in configuration
space is set
• If enabled (by the SERR Enable bit and the SERR on Abort Enable bit in the
function’s configuration space), then the Signaled System Error bit in configuration
bit is set and the internal SERR signal is asserted
26.9.2 Host Interface Parity Errors
In the event of parity errors on the host-side interface, the EHC is required to respond
as shown in the following table.
The EHC is accessible as a target after the parity errors are detected (assuming that
Table 26-53. Host Interface Parity Errors (Sheet 1 of 2)
Input Scenario
Resulting Behavior
Event
Downbound
Request
Command Parity
Error
Parity
Error
Resp
0
1
1
SERR# En
(CMD
register,
bit 8)
DPE
(DSR
register,
bit 15)
Master DPE
(DSR
register, bit
8)
X
1
0
0
1
0
1
1
0
Host
System
Error
(USB
Status)
0
1
1
Notes
Do take the cycle, as normal.
Do not take the cycle (master abort).
No SERR# generated
Do not take the cycle (master abort).
SERR# generated
Intel^® EP80579 Integrated Processor Product Line Datasheet
1028
August 2009
Order Number: 320066-003US